Tsukamoto Yasumasa

发表

A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry

Fujiwara Hidehiro, Nii Koji, Yabuuchi Makoto, 2013 .

A 45nm 0.6V Cross-Point 8T SRAM with Negative Biased Read/Write Assist

Nii Koji, Yabuuchi Makoto, Tsukamoto Yasumasa, 2010 .

心不全の臨床心不全の治療非薬物治療左室補助人工心臓(LVAD)・補助人工心臓(VAD)

Tsukamoto Yasumasa, Sakata Yasushi, 2016 .

Worst-Case Ananlysis to Obtain Stable Read/Write DC Margin of High Density 6T-SRAM-Array with Local Vth Variability

Nii Koji, Yabuuchi Makoto, Tsukamoto Yasumasa, 2006 .

Write-/Read- Disturb Issues and Circuit Solutions

Tanaka Shinji, Tanaka Koji, Shimazaki Yasuhisa, 2012 .

[Invited]Robust Design of Embedded SRAM on Deep-submicron Technology

Nii Koji, Yabuuchi Makoto, Tsukamoto Yasumasa, 2008 .

A Stable Chip-ID Generating Physical Uncloneable Function Using Random Address Errors in SRAM

Fujiwara Hidehiro, Nii Koji, Nakano Hirofumi, 2012 .

20nm High-Density Single-Port and Dual-Port SRAMs with Wordline-Voltage-Adjustment System for Read/Write Assists

Morimoto Masao, Nii Koji, Yabuuchi Makoto, 2015 .

A 65 nm Embedded SRAM with Wafer Level Burn-In Mode, Leak-Bit Redundancy and E-trim Fuse for Known Good Die

Nii Koji, Yabuuchi Makoto, Tsukamoto Yasumasa, 2007 .

Reduction of SRAM Standby Leakage utlizing All Digital Current Comparator

Tanaka Koji, Komatsu Shigenobu, Morimoto Masao, 2013 .

A 65 nm Ultra-High-Density Dual-port SRAM with 0.71um2 8T-cell for SoC

Nii Koji, Yabuuchi Makoto, Tsukamoto Yasumasa, 2006 .