Ishii Yuichiro

发表

A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry

Fujiwara Hidehiro, Nii Koji, Yabuuchi Makoto, 2013 .

40 nm Dual-port and Two-port SRAMs for Automotive MCU Applications under the Wide Temperature Range of -40 to 170℃ with Test Screening Against Write Disturb Issues

Nii Koji, Ishii Yuichiro, Yokoyama Yoshisato, 2015 .

A 6.05-Mb/mm2 16-nm FinFET Double Pumping 1W1R 2-port SRAM with 313ps Read Access Time

Tanaka Shinji, Morimoto Masao, Nii Koji, 2017 .

A dynamic/static SRAM power management scheme for DVFS and AVS in advanced automotive infotainment SoCs

Tanaka Shinji, Nii Koji, Fukuoka Kazuki, 2016 .

Write-/Read- Disturb Issues and Circuit Solutions

Tanaka Shinji, Tanaka Koji, Shimazaki Yasuhisa, 2012 .

A 28-nm dual-port SRAM macro with active bitline equalizing circuitry against write disturb issue

Fujiwara Hidehiro, Nii Koji, Ishii Yuichiro, 2011 .

A Cost Effective Test Screening Method on 40-nm 4-Mb Embedded SRAM for Low-power MCU

Tanaka Koji, Nii Koji, Ishii Yuichiro, 2016 .

A Dynamic Power Reduction in Synchronous 2RW 8T Dual-Port SRAM by Adjusting Wordline Pulse Timing with Same/Different Row Access Mode

Nii Koji, Ishii Yuichiro, Yokoyama Yoshisato, 2018 .

40nm ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU

Nii Koji, Ishii Yuichiro, Yanagisawa Kazumasa, 2014 .