Yung-Chuan Jiang

Reduced Communication Costs via Network Flow and Scheduling for Partitions of Dynamically Reconfigurable FPGAs

Jhing-Fa Wang, Yung-Chuan Jiang, 2010, J. Inf. Sci. Eng..

A minimum communication cost algorithm for dynamically reconfigurable computing system

Yen-Tai Lai, Yung-Chuan Jiang, Y. Lai, 2007 .

BDD decomposition for mixed CMOS/PTL logic circuit synthesis

Yen-Tai Lai, Yung-Chuan Jiang, Hong-Ming Chu, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Minimum Communication Cost Approaches for Dynamically Reconfigurable FPGA

Yung-Chuan Jiang, Yung-Chuan Jiang, 2007, 2007 International Symposium on Signals, Circuits and Systems.

Parallel reconfigurable computing and its application to hidden Markov model

Jechang Jeong, Yung-Chuan Jiang, Anand Paul, 2010 .

A parallel partitioning algorithm for parallel reconfigurable computing

Yen-Tai Lai, Yung-Chuan Jiang, 2007 .

Temporal Partitioning Data Flow Graphs for Dynamically Reconfigurable Computing

Jhing-Fa Wang, Yung-Chuan Jiang, Jhing-Fa Wang, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Parallel Reconfigurable Computing-Based Mapping Algorithm for Motion Estimation in Advanced Video Coding

Jhing-Fa Wang, Jar-Ferr Yang, Anand Paul, 2012, TECS.

Computation Aware Scheme for Visual Signal Processing

Jhing-Fa Wang, Anand Paul, Yung-Chuan Jiang, 2010, J. Softw..

Dynamic Parallel Computing Architecture for Video Processing

Jhing-Fa Wang, K. Bharanitharan, Yung-Chuan Jiang, 2010 .