Ki-Seok Chung

发表

A static estimation technique of power sensitivity in logic circuits

Taewhan Kim, Ki-Seok Chung, C.L. Liu, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Acceleration of artificial neural network using cores specialized in matrix multiplication in GPU

Ki-Seok Chung, Sang-Soo Park, Won-Hyuk Lee, 2020 .

An algorithm for synthesis of system-level interface circuits

C. Liu, Rajesh K. Gupta, Ki-Seok Chung, 1996, Proceedings of International Conference on Computer Aided Design.

Benefits of the big . LITTLE Architecture

Ki-Seok Chung, Kisuk Chung, Taehoon Kim, 2012 .

Stage-based frame-partitioned parallelization of H.264/AVC decoding

Ki-Seok Chung, Won-Jin Kim, Keol Cho, 2010, IEEE Transactions on Consumer Electronics.

Mitigating Row-hammering by Adapting the Probability of Additional Row Refresh

Ki-Seok Chung, Jeonghyun Woo, 2019, 2019 IEEE 4th International Conference on Technology, Informatics, Management, Engineering & Environment (TIME-E).

Parallelizing Bank-level Fine Granularity Refresh with Column Access Operation using Split Row Buffer

Ki-Seok Chung, Min-Kyu Lee, 2018 .

Simplified 2-Dimensional Scaled Min-Sum Algorithm for LDPC Decoder

Wang-Heon Lee, Ki-Seok Chung, Keol Cho, 2017 .

Implementation of a CNN accelerator on an Embedded SoC Platform using SDSoC

Ki-Seok Chung, Sang-Soo Park, Kyeong-Bin Park, 2018, ICDSP 2018.

Symmetric Adiabatic Logic Circuits against Differential Power Analysis

Dong Kyue Kim, Ki-Seok Chung, Byong-Deok Choi, 2010 .

HammerFilter: Robust Protection and Low Hardware Overhead Method for RowHammer

Ki-Seok Chung, Kwangrae Kim, Jeonghyun Woo, 2021, 2021 IEEE 39th International Conference on Computer Design (ICCD).

Low power multiplexer decomposition

Chien-Liang Liu, Hon Wai Leong, Unni Narayanan, 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

Local transformation techniques for multi-level logic circuits utilizing circuit symmetries for power reduction

C.L. Liu, Ki-Seok Chung, Ki-Seok Chung, 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

Design of a Low Power Reconfigurable DSP with Fine-Grained Clock Gating

Ki-Seok Chung, Chan-Min Jung, Young-Geun Lee, 2007 .

A stepwise refinement data path synthesis procedure for easy testability

Taewhan Kim, C. L. Liu, K.-S. Chung, 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

Enhanced bus invert encodings for low-power

Taewhan Kim, Ki-Seok Chung, U. Narayanan, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Decomposition of Bus-Invert Coding for Low-Power I/O

Sungpack Hong, Ki-Seok Chung, Taewhan Kim, 2000, J. Circuits Syst. Comput..

Thermal sensor allocation and placement for reconfigurable systems

Taewhan Kim, Bontae Koo, Nak-Woong Eum, 2009, TODE.

Multi-way interactive capacitive touch system with palm rejection of active stylus for 86” touch screen panels

Oh-Kyong Kwon, Seung-Hwan Lee, Seong-Kwan Hong, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

Selection-based Low-cost Check Node Operation for Extended Min-Sum Algorithm

Chung Ki-Seok, Kyeong-Bin Park, Ki-Seok Chung, 2021, KSII Trans. Internet Inf. Syst..

A Low-Complexity Adaptive Extended Min-Sum Algorithm for Non-Binary LDPC Codes

Ki-Seok Chung, Kyeong-Bin Park, Min-Ho Kim, 2020, 2020 5th International Conference on Computational Intelligence and Applications (ICCIA).

Optimization of FPGA-based LDPC decoder using high-level synthesis

Ki-Seok Chung, Kyeong-Bin Park, Geon Choi, 2018, ICCIP '18.

Self-Adaptive Termination Check of Min-Sum Algorithm for LDPC Decoders Using the First Two Minima

Ki-Seok Chung, Keol Cho, Ki-Seok Chung, 2017, KSII Trans. Internet Inf. Syst..

Implementation of an LDPC decoder on a heterogeneous FPGA-CPU platform using SDSoC

Ki-Seok Chung, Keol Cho, Si-Dong Roh, 2016, 2016 IEEE Region 10 Conference (TENCON).

Self-Adaptive Scaled Min-Sum Algorithm for LDPC Decoders Based on Delta-Min

Ki-Seok Chung, Keol Cho, Ki-Seok Chung, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Parallel LDPC Decoding on a Heterogeneous Platform using OpenCL

Ki-Seok Chung, Jung-Hyun Hong, Joo-Yul Park, 2016, KSII Trans. Internet Inf. Syst..

Dynamic voltage and frequency scaling scheme for an adaptive LDPC decoder using SNR estimation

Ki-Seok Chung, Joo-Yul Park, Youngho Ahn, 2013, EURASIP J. Wirel. Commun. Netw..

Parallel LDPC decoding using CUDA and OpenMP

Ki-Seok Chung, Joo-Yul Park, Ki-Seok Chung, 2011, EURASIP J. Wirel. Commun. Netw..

Overlapped message passing technique with resource sharing for high speed CMMB LDPC decoder

Ki-Seok Chung, Joo-Yul Park, Ki-Seok Chung, 2011, IEEE Transactions on Consumer Electronics.

LDPC decoding for CMMB utilizing OpenMP and CUDA parallelization

Ki-Seok Chung, Joo-Yul Park, Ki-Seok Chung, 2011, The 17th Asia Pacific Conference on Communications.

An adaptive low-power LDPC decoder using SNR estimation

Ki-Seok Chung, Joo-Yul Park, Ki-Seok Chung, 2011, EURASIP J. Wirel. Commun. Netw..

Memory efficient multi-rate regular LDPC decoder for CMMB

Ki-Seok Chung, Joo-Yul Park, So-Jin Lee, 2009, IEEE Transactions on Consumer Electronics.

Iterative Pseudo-Soft-Reliability-Based Majority-Logic Decoding for NAND Flash Memory

Ki-Seok Chung, Kyeong Bin Park, Ki-Seok Chung, 2021, IEEE Access.

CENNA: Cost-Effective Neural Network Accelerator

Sang-Soo Park, Ki-Seok Chung, Ki-Seok Chung, 2020 .

Predictive power aware management for embedded mobile devices

Ki-Seok Chung, Chan-Min Jung, Young-Si Hwang, 2008, 2008 Asia and South Pacific Design Automation Conference.

CONNA: Configurable Matrix Multiplication Engine for Neural Network Acceleration

Ki-Seok Chung, Sang-Soo Park, 2022, Electronics.

Effective Verification Environment using SoC Platform

Jong-Wha Chong, Ki-Seok Chung, Byung-Gyu Ahn, 2006 .