Changliang Qin

Integration of Highly Strained SiGe in Source and Drain with HK and MG for 22 nm Bulk PMOS Transistors

Tianchun Ye, Jun Xu, Chao Zhao, 2017, Nanoscale Research Letters.

Study of SiGe selective epitaxial process integration with high-k and metal gate for 16/14nm nodes FinFET technology

Tianchun Ye, Ping Yang, Jun Luo, 2016 .

Integration Issue of Tensile SiN Liner for Dual Stress Liner(DSL) in Gate-Last High-k/Metal Gate(HKMG) Process Flow

Qiang Xu, Tao Yang, Peizhen Hong, 2013 .

Optimization of SiGe selective epitaxy for source/drain engineering in 22 nm node complementary metal-oxide semiconductor (CMOS)

Chao Zhao, Jiang Yan, Changliang Qin, 2013 .

Two methods of tuning threshold voltage of bulk FinFETs with replacement high-k metal-gate stacks

Tianchun Ye, Jun Luo, Changliang Qin, 2017 .

Fabrication and Characterization of p-Channel Charge Trapping Type FOI-FinFET Memory with MAHAS Structure

Jie Gu, Huaxiang Yin, Changliang Qin, 2017 .

FOI FinFET with ultra-low parasitic resistance enabled by fully metallic source and drain formation on isolated bulk-fin

Tianchun Ye, Junjie Li, Chao Zhao, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).