Jiang Yan

发表

Integration of Highly Strained SiGe in Source and Drain with HK and MG for 22 nm Bulk PMOS Transistors

Tianchun Ye, Jun Xu, Chao Zhao, 2017, Nanoscale Research Letters.

Study of SiGe selective epitaxial process integration with high-k and metal gate for 16/14nm nodes FinFET technology

Tianchun Ye, Ping Yang, Jun Luo, 2016 .

Influence of Rapid Thermal Annealing on Ge-Si Interdiffusion in Epitaxial Multilayer Ge0.3Si0.7/Si Superlattices with Various GeSi Thicknesses

Guilei Wang, H. Yin, Jiang Yan, 2018 .

Carbon-free Cu 2 ZnSn(S,Se) 4 film prepared via a non-hydrazine route

W. Lijun, Jiang Yan, Hu Jinsong, 2014 .

Effect of process parameters on sidewall damage in deep silicon etch

Jiang Yan, Lingkuan Meng, Jiang Yan, 2015 .

A Novel Nanofabrication Technique of Silicon-Based Nanostructures

Yayi Wei, Jianfeng Gao, Xiaobin He, 2016, Nanoscale Research Letters.

Transistor gate line roughness formation and reduction in sub-30-nm gate patterning using multilayer hard mask structure

Xiaobin He, Junfeng Li, Jiang Yan, 2014 .

CMOS-Compatible Top-Down Fabrication of Periodic SiO2 Nanostructures using a Single Mask

Yayi Wei, Jianfeng Gao, Xiaobin He, 2015, Nanoscale Research Letters.

Electrical Properties of Ultrathin Hf-Ti-O Higher k Gate Dielectric Films and Their Application in ETSOI MOSFET

Jiang Yan, Wenwu Wang, Jun Du, 2016, Nanoscale Research Letters.

Si Nanowire Biosensors Using a FinFET Fabrication Process for Real Time Monitoring Cellular Ion Actitivies

Q. Han, R. Zhao, Junfeng Li, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Diamond-Like Carbon Thin Films with Extremely High Compressive Stress (>8~12GPa) for Advanced CMOS Strain Engineering

Tianchun Ye, H. Yin, Jiang Yan, 2012 .

A straightforward and CMOS-compatible nanofabrication technique of periodic SiO2 nanohole arrays

Yayi Wei, Jianfeng Gao, Xiaobin He, 2015, Nanotechnology.

Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process*

Tianchun Ye, Jiang Yan, Huilong Zhu, 2017 .

A New Solution to the Ni-fill issue for Silicide-last Process

Jun Luo, Jiang Yan, S. Mao, 2013 .

Effects of a carbon implant on thermal stability of Ni0.95(Pt0.05)Si

Jiang Yan, Qingzhu Zhang, Zhaoyun Tang, 2015 .

Cost-effective amorphous silicon hard mask patterning sub-45nm contact trench

Jianfeng Gao, Xiaobin He, Jiang Yan, 2014, IEEE International Conference on Solid-State and Integrated Circuit Technology.

Gate patterning in 14 nm and beyond nodes: from planar devices to three dimensional Finfet devices

Yayi Wei, Xiaobin He, Junfeng Li, 2016 .

Innovatively composite hard mask to feature sub-30 nm gate patterning

Jun Luo, Xiaobin He, Junfeng Li, 2014 .

Mechanism study of sidewall damage in deep silicon etch

Jiang Yan, Lingkuan Meng, Jiang Yan, 2014 .

Facile fabrication of Si-based nanostructures

Jiang Yan, Lingkuan Meng, Jiang Yan, 2017, Advanced Lithography.

High-Performance Silicon Nanowire Gate-All-Around nMOSFETs Fabricated on Bulk Substrate Using CMOS-Compatible Process

Jiang Yan, Chao Zhao, J. Niu, 2010, IEEE Electron Device Letters.

Optimization of SiGe selective epitaxy for source/drain engineering in 22 nm node complementary metal-oxide semiconductor (CMOS)

Chao Zhao, Jiang Yan, Changliang Qin, 2013 .

Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

Jun Luo, Jiang Yan, Huajie Zhou, 2011 .

Study of Electrical Behavior of Hf-Ti-O Higher-k Dielectric for ETSOI MOSFET Application

Jiang Yan, Jun Du, Y. Xiong, 2015 .

O2 plasma treated biosensor for enhancing detection sensitivity of sulfadiazine in a high-к HfO2 coated silicon nanowire array

H. Yin, Jiang Yan, Wenwu Wang, 2020 .

pMOSFETs Featuring ALD W Filling Metal Using SiH4 and B2H6 Precursors in 22 nm Node CMOS Technology

Tianchun Ye, Chao Zhao, Huilong Zhu, 2017, Nanoscale Research Letters.

Study of HKMG Stack Interface Engineer Applicable to 22nm/16nm Finfet Mosfet

Ying Luo, Chao Zhao, Junfeng Li, 2014 .

Investigation of TaN as the wet etch stop layer for HKMG-last integration in the 22 nm and beyond nodes CMOS technology

Tianchun Ye, Jun Luo, Jianfeng Gao, 2015 .

Application of Atomic Layer Deposition Tungsten (ALD W) as Gate Filling Metal for 22 nm and Beyond Nodes CMOS Technology

Tianchun Ye, Chao Zhao, Jing Xu, 2013 .

Study on influences of TiN capping layer on time-dependent dielectric breakdown characteristic of ultra-thin EOT high-k metal gate NMOSFET with kMC TDDB simulations*

Tianchun Ye, Yefeng Xu, Junfeng Li, 2016 .

Study of Hf-Ti-O Thin Film as High-k Gate Dielectric and Application for ETSOI MOSFETs

Jiang Yan, Jun Du, Y. Xiong, 2016, Journal of Electronic Materials.

FOI FinFET with ultra-low parasitic resistance enabled by fully metallic source and drain formation on isolated bulk-fin

Tianchun Ye, Junjie Li, Chao Zhao, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Influence of the hard masks profiles on formation of nanometer Si scalloped fins arrays

H. Yin, Jiang Yan, H. Tu, 2018, Microelectronic Engineering.

Planar Bulk MOSFETs With Self-Aligned Pocket Well to Improve Short-Channel Effects and Enhance Device Performance

Tianchun Ye, Q. Liang, Hongyu Yu, 2015, IEEE Transactions on Electron Devices.

Optimization of zero-level interlayer dielectric materials for gate-all-around silicon nanowire channel fabrication in a replacement metal gate process

Guilei Wang, H. Yin, Jiang Yan, 2021 .

X-ray irradiation-induced degradation in Hf0.5Zr0.5O2 fully depleted silicon-on-insulator n-type metal oxide semiconductor field-effect transistors

Jiang Yan, Qing-zhu Zhang, Yudong Li, 2020, Rare Metals.