Ye-Ram Kim

Extraction of source/drain resistivity parameters optimized for double-gate FinFETs

Jun-Sik Yoon, E. Jeong, Sanghyun Lee, 2015 .

Impact of the spacer dielectric constant on parasitic RC and design guidelines to optimize DC/AC performance in 10-nm-node Si-nanowire FETs

Jun-Sik Yoon, E. Jeong, Sanghyun Lee, 2015 .

Investigation of RC parasitics considering middle-of-the-line in si-bulk FinFETs for Sub-14-nm node logic applications

Jun-Sik Yoon, E. Jeong, Ye-Ram Kim, 2015, IEEE Transactions on Electron Devices.

Simple S/D Series Resistance Extraction Method Optimized for Nanowire FETs

Sungho Kim, Yoon-Ha Jeong, Dong-Won Kim, 2013, IEEE Electron Device Letters.

Investigation of Low-Frequency Noise in p-type Nanowire FETs: Effect of Switched Biasing Condition and Embedded SiGe Layer

Dong-Won Kim, Jun-Sik Yoon, E. Jeong, 2014, IEEE Electron Device Letters.

Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node

Jun-Sik Yoon, E. Jeong, Ye-Ram Kim, 2015, IEEE Electron Device Letters.