T. Nishimura

发表

Analytical Device Model of SOI MOSFETs Including Self-Heating Effect

K. Taniguchi, Y. Yamaguchi, N. Yasuda, 1991 .

Simulation and two-dimensional analytical modeling of subthreshold slope in ultrathin-film SOI MOSFETs down to 0.1 mu m gate length

Hans-Oliver Joachim, Y. Inoue, Y. Yamaguchi, 1993 .

Source-to-drain breakdown voltage improvement in ultrathin-film SOI MOSFET's using a gate-overlapped LDD structure

Y. Inoue, T. Iwamatsu, H. Oda, 1994 .

Subthreshold Slope in Ultra Thin-Film SOI MOSFET's and Its Two-Dimensional Analytical Modeling down to 0.1μm Gate Length

K. Tsukamoto, Y. Yamaguchi, Y. Yamaguchi, 1992 .

Soft error susceptibility and immune structures in dynamic random access memories (DRAMs) investigated by nuclear microprobes

T. Kishimoto, S. Satoh, Yoshikazu Ohno, 1996 .

oft Error Susceptibility and Immune Struc in Dynamic andom Access 's) Investigated by Nucle

K. Sonoda, H. Miyoshi, H. Sayama, 1996 .

Fabrication of an optical directional coupler of CdTe by electron beam lithography and ion etching

S. Namba, T. Nishimura, H. Aritome, 1980 .

Study of current induced magnetic domain wall movement with extremely low energy consumption by micromagnetic simulation

K. Ishikawa, Y. Inoue, M. Inuishi, 2011, 2011 International Conference on Simulation of Semiconductor Processes and Devices.

Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's (Special Issue on ULSI Memory Technology)

Hideto Hidaka, Katsuhiro Suma, Kazuyasu Fujishima, 1996 .

Self-aligned silicide technology for ultra-thin SIMOX MOSFETs

Y. Akasaka, Y. Yamaguchi, K. Fujibayashi, 1992 .

Analysis of effect of gate oxidation at SiC MOS interface on threshold-voltage shift using deep-level transient spectroscopy

S. Nakata, M. Furuhashi, T. Nishimura, 2015 .

A high speed 0.6- mu m 16 K CMOS gate array on a thin SIMOX film

Katsuhiro Tsukamoto, Masahiro Shimizu, Y. Yamaguchi, 1993 .

Integration of BST thin film for DRAM fabrication

T. Nishimura, T. Horikawa, T. Okudaira, 1995 .

Investigation of Stacking Faults Affecting on Reverse Leakage Current of 4H-SiC Junction Barrier Schottky Diodes Using Device Simulation

S. Nakata, T. Nishimura, Yuki Nakamura, 2014 .

A bipolar 18K-gate variable size cell masterslice

M. Kohara, K. Sakaue, T. Hirao, 1986 .

An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

T. Eimori, Y. Inoue, T. Iwamatsu, 1994, IEEE International Solid-State Circuits Conference.

CAD-compatible high-speed CMOS/SIMOX gate array using field-shield isolation

T. Iwamatsu, Yasuo Inoue, N. Tsubouchi, 1995 .

Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM

T. Eimori, Y. Yamaguchi, M. Yamada, 1999 .