J. Chung

发表

Measurement and modeling of self-heating in SOI nMOSFET's

Kenneth E. Goodson, Dimitri A. Antoniadis, L. T. Su, 1994 .

Dimitri A. Antoniadis, L. T. Su, M. J. Sherony, 1994 .

Two-stage hot-carrier degradation and its impact on submicrometer LDD NMOSFET lifetime prediction

J. Chung, V. Chan, 1993 .

A model for hot-electron-induced MOSFET linear-current degradation based on mobility reduction due to interface-state generation

C. Hu, P. Ko, J. Chung, 1991 .

Low-voltage hot-electron currents and degradation in deep-submicrometer MOSFETs

C. Hu, P. Ko, J. Moon, 1990 .

The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes

D. Boning, J. Chung, B. Stine, 1998 .

Rapid characterization and modeling of pattern-dependent variation in chemical-mechanical polishing

O. S. Nakagawa, D. Boning, J. Chung, 1998 .

Statistical Metrology: Tools for Understanding Variation

Duane S. Boning, J. E. Chung, D. Boning, 1996 .

Comparison of Oxide Planarization Pattern Dependencies between Two Different CMP Tools Using Statistical Metrology

O. S. Nakagawa, D. Boning, J. Chung, 1996 .

Buried-oxide charge trapping induced performance degradation in fully-depleted ultra-thin SOI p-MOSFET's

J. Chung, N. Annamalai, Hua-Fang Wei, 1996 .

Low-temperature furnace-grown reoxidized nitrided oxide gate dielectrics as a barrier to boron penetration

C. Sodini, D. Antoniadis, J. Chung, 1992, IEEE Electron Device Letters.

Ultrathin furnace reoxidized nitrided oxide gate dielectrics for extreme submicrometer CMOS technology

C. Sodini, D. Antoniadis, J. Chung, 1992, 1992 International Technical Digest on Electron Devices Meeting.

Intrinsic transconductance extraction for deep-submicrometer MOSFETs

Gary S. May, J. Chung, Ping Keung Ko, 1989 .

Suppression of parasitic bipolar effects and off-state leakage in fully-depleted SOI n-MOSFET's using Ge-implantation

F. Namavar, J. Chung, N. Kalkhoran, 1995 .

Deep-submicrometer MOS device fabrication using a photoresist-ashing technique

A.T. Wu, T.Y. Chan, T. Chan, 1988, IEEE Electron Device Letters.

Analysis and decomposition of spatial variation in integrated circuit processes and devices

Duane S. Boning, J. E. Chung, B. E. Stine, 1997 .

A model for SIMOX buried-oxide high-field conduction

J. Chung, J. Yoon, G. Brown, 1996 .

A CLOSED-FORM ANALYTIC MODEL FOR ILD THICKNESS VARIATION IN CMP PROCESSES

Duane S. Boning, J. E. Chung, Iqbal Ali, 1997 .

The effects of low-angle off-axis substrate orientation on MOSFET performance and reliability

Ping-Keung Ko, Chenming Hu, Jone-Fang Chen, 1991 .

Low-voltage hot-electron currents and degradation in deep-submicrometer MOSFETs

C. Hu, P. Ko, J. Moon, 1989, 27th Annual Proceedings., International Reliability Physics Symposium.

Assessing circuit-level hot-carrier reliability

W. Jiang, H. Le, T. E. Kopley, 1998, 1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173).

Statistical metrology for interlevel dielectric thickness variation

Duane S. Boning, J. E. Chung, Keh-Jeng Chang, 1994, Advanced Lithography.

Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's

L. T. Su, D. Antoniadis, J. B. Jacobs, 1994, IEEE Electron Device Letters.

Performance and reliability design issues for deep-submicrometer MOSFETs

Chenming Calvin Hu, Ping-Keung Ko, J. E. Moon, 1991 .

Wafer Scale Variation of Planarization Length in Chemical Mechanical Polishing

D. Boning, J. Yoon, J. Chung, 2000 .

Beating the heat [CMOS hot-carrier reliability]

J. E. Chung, Huy Le, D. S. Sugiharto, 1998 .

Design guidelines for deep-submicrometer MOSFETs

Gary S. May, Ping-Keung Ko, J. E. Moon, 1988, Technical Digest., International Electron Devices Meeting.