Jaw-Jung Shin

Novel 20nm hybrid SOI/bulk CMOS technology with 0.183/spl mu/m/sup 2/ 6T-SRAM cell by immersion lithography

Tsai-Sheng Gau, Jaw-Jung Shin, Chien-Chao Huang, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

45nm node planar-SOI technology with 0.296μm2 6T-SRAM cell

Chenming Hu, Mong-Song Liang, Fu-Liang Yang, 2004, VLSIT 2004.

Gratinglike modulation of GaAs/AlGaAs quantum well intermixing fabricated with laser interference

Jaw-Jung Shin, C. C. Yang, Yih J. Chang, 1998 .