Prithviraj Pachal

Analytical model of a novel double gate metal-infused stacked gate-oxide tunnel field-effect transistor (TFET) for low power and high-speed performance

S. Sarkar, S. Guha, Prithviraj Pachal, 2020 .

Performance Analysis of Underlap Double Gate Oxide Stacked Junctionless MOSFET for Analog and RF Applications

D. De, Prithviraj Pachal, M. Chanda, 2019, 2019 TEQIP III Sponsored International Conference on Microwave Integrated Circuits, Photonics and Wireless Networks (IMICPW).

Heterojunction Negative-Capacitance Tunnel-FET as a Promising Candidate for Sub-0.4V VDD Digital Logic Circuits

S. Guha, Prithviraj Pachal, 2021, IEEE Transactions on Nanotechnology.

Effect of Body Thickness on Device Performance of Graded Channel Tri-Metal Double Gate Stack Gate TFET

S. Sarkar, S. Guha, Prithviraj Pachal, 2020, 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS).

Design and Analog/RF Performance Analysis of a Novel Symmetric Raised-Channel SiGe Heterojunction Tunnel Field-Effect Transistor (TFET)

S. Guha, Prithviraj Pachal, 2021, Silicon.

Exploring the Feasibility of Implementing Negative-Capacitance Tunnel-FET (NC-TFET) in Low-Power Digital Circuits

S. Guha, Prithviraj Pachal, 2022, 2022 IEEE VLSI Device Circuit and System (VLSI DCS).