S. Dubey

发表

Modeling of Sub Threshold Current and Sub Threshold Swing of Short- Channel Fully-Depleted SOI MOSFET with Back-Gate Control

R. Mishra, S. Dubey, 2017 .

Analytical Modeling of Potential Distribution and Threshold Voltage of Gate Underlap DG MOSFETs with a Source/Drain Lateral Gaussian Doping Profile

Satyabrata Jit, Sarvesh Dubey, Balraj Singh, 2016, Journal of Electronic Materials.

Analytical modeling of threshold voltage for symmetrical silicon nano-tube field-effect-transistors (Si-NT FETs)

P. Tiwari, S. Jit, S. Dubey, 2016 .

Quasi-3D subthreshold current and subthreshold swing models of dual-metal quadruple-gate (DMQG) MOSFETs

P. Tiwari, S. Dubey, V. R. Samoju, 2015 .

Analytical subthreshold current and subthreshold swing models of short-channel dual-metal-gate (DMG) fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs

Satyabrata Jit, Sarvesh Dubey, Pramod Kumar Tiwari, 2014 .

Analog and radio-frequency (RF) performance evaluation of fully-depleted (FD) recessed-source/drain (Re-S/D) SOI MOSFETs

Sarvesh Dubey, Pramod Kumar Tiwari, Gopi Krishna Saramekala, 2014 .

An Analytical Study of Ion Implanted Strained-Si on SOI MOSFETs for Optimizing Switching Characteristics

S. Jit, S. Dubey, Mirgender Kumar, 2014 .

An analytical model of threshold voltage for short-channel double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs

Satyabrata Jit, Sarvesh Dubey, Pramod Kumar Tiwari, 2013 .

An Analytical Model for the Threshold Voltage of Short-Channel Double-Material-Gate (DMG) MOSFETs with a Strained-Silicon (s-Si) Channel on Silicon-Germanium (SiGe) Substrates

Sarvesh Dubey, Pramod Kumar Tiwari, Abirmoya Santra, 2013 .

An analytical threshold voltage model for a short-channel dual-metal-gate (DMG) recessed-source/drain (Re-S/D) SOI MOSFET

Satyabrata Jit, Sarvesh Dubey, Pramod Kumar Tiwari, 2013 .

An analytical surface potential modeling of fully-depleted symmetrical double-gate (DG) strained-Si MOSFETs including the effect of interface charges

P. Tiwari, S. Bhushan, S. Dubey, 2013, 2013 Students Conference on Engineering and Systems (SCES).

An analytical modeling of interface charge induced effects on subthreshold current and subthreshold swing of strained-Si (s-Si) on Silicon-Germinium-on-Insulator (SGOI) MOSFETs

P. Tiwari, S. Jit, S. Dubey, 2012, 2012 5th International Conference on Computers and Devices for Communication (CODEC).

An Analytical Study of Short-Channel Effects of Strained-Si on Silicon- Germanium-on-Insulator (SGOI) MOSFETs Including Interface Charges

P. Tiwari, S. Jit, S. Dubey, 2012 .

AN ANALYTICAL SURFACE POTENTIAL MODEL FOR STRAINED-Si ON SILICON- GERMANIUM MOSFET INCLUDING THE EFFECTS OF INTERFACE CHARGES

P. Tiwari, S. Jit, S. Bhushan, 2012 .

A two-dimensional analytical model for threshold voltage of short-channel triple-material double-gate metal-oxide-semiconductor field-effect transistors

Satyabrata Jit, Sarvesh Dubey, Pramod Kumar Tiwari, 2010 .

A two-dimensional model for the potential distribution and threshold voltage of short-channel double-gate metal-oxide-semiconductor field-effect transistors with a vertical Gaussian-like doping profile

Satyabrata Jit, Sarvesh Dubey, Pramod Kumar Tiwari, 2010 .

A Two-Dimensional Model for the Surface Potential and Subthreshold Current of Doped Double-Gate (DG) MOSFETs with a Vertical Gaussian-Like Doping Profile

Satyabrata Jit, Sarvesh Dubey, Pramod Kumar Tiwari, 2010 .

A two-dimensional model for the subthreshold swing of short-channel double-gate metal–oxide–semiconductor field effect transistors with a vertical Gaussian-like doping profile

Satyabrata Jit, Sarvesh Dubey, Pramod Kumar Tiwari, 2011 .

Two-dimensional modeling of subthreshold current and subthreshold swing of double-material-gate (DMG) strained-Si (s-Si) on SGOI MOSFETs

Satyabrata Jit, Sarvesh Dubey, Pramod Kumar Tiwari, 2013 .

A rigorous simulation based study of gate misalignment effects in gate engineered double-gate (DG) MOSFETs

P. Tiwari, S. Jit, S. Bhushan, 2013 .

Investigating the Possibility to Extend Planar Technology to 10 nm Scale with UTBB DMG SSOI MOSFETs

S. Dubey, Mirgender Kumar, Vivek Mishra, 2019, 2019 International Conference on Cutting-edge Technologies in Engineering (ICon-CuTE).

Analytical modeling and simulation of subthreshold characteristics of back-gated SSGOI and SSOI MOSFETs: A comparative study

P. Tiwari, S. Jit, S. Dubey, 2013 .

Subthreshold current model for short-channel double-gate (DG) MOSFETs with vertical Gaussian doping profile

P. Tiwari, S. Jit, S. Dubey, 2010 .

Design and investigation of ZnO based thin film transistors for high-speed AMLCD pixel circuit applications

B. Kumar, P. Tiwari, S. Dubey, 2021, Superlattices and Microstructures.

MOSFET based circuit implementation in the subthreshold regime of device operation is the current trend in low-power VLSI design. For proper design of such type of circuits, threshold voltage determination of DG MOSFET

S. Jit, S. Dubey, 2022 .

Electronic Noise Analysis of Source-Engineered Phosphorene/Si Heterojunction Dopingless Tunnel-FET

S. Dubey, Kunal Singh, Rahul Misra, 2022, Silicon.

Investigating linearity and effect of temperature variation on analog/RF performance of dielectric pocket high-k double gate-all-around (DP-DGAA) MOSFETs

P. Tiwari, S. Dubey, Kunal Singh, 2020, Applied Physics A.

An analytical model of threshold voltage for short-channel double-material-gate (DMG) strained-Si (s-Si) on Silicon-Germanium-on-Insulator (SGOI) MOSFETs

P. Tiwari, S. Jit, S. Dubey, 2012, Journal of Computational Electronics.

Impact of Different Gate Dielectric Materials on Analog/RF Performance of Dielectric-Pocket Double Gate-All-Around (DP − DGAA) MOSFETs

S. Dubey, Himanshi Awasthi, Rajeev Gupta, 2022, Silicon.

Analytical subthreshold current and subthreshold swing models of short-channel dual-metal-gate (DMG) fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs

P. Tiwari, S. Jit, S. Dubey, 2014, Journal of Computational Electronics.

Analytical modeling of subthreshold current and subthreshold swing of short-channel triple-material double-gate (TM-DG) MOSFETs

Satyabrata Jit, Sarvesh Dubey, Pramod Kumar Tiwari, 2012 .

Electronic Noise Analysis of Source-Engineered Phosphorene/Si Heterojunction Dopingless Tunnel-FET

S. Dubey, Kunal Singh, Rahul Misra, 2022, Silicon.

Impact of Temperature on Analog/RF Performance of Dielectric Pocket Gate-all-around (DPGAA) MOSFETs

S. Dubey, Himanshi Awasthi, Nitish Kumar, 2020, Silicon.

Evolution of Multigate MOSFETs

S. Dubey, Sushmita Jaiswal, 2017 .

On-current modeling of short-channel double-gate (DG) MOSFETs with a vertical Gaussian-like doping profile

Satyabrata Jit, Sarvesh Dubey, Pramod Kumar Tiwari, 2013 .

Modeling the threshold voltage of core-and-outer gates of ultra-thin nanotube Junctionless-double gate-all-around (NJL-DGAA) MOSFETs

Nitish Kumar, Sarvesh Dubey, Vaibhav Purwar, 2021, Microelectron. J..

An Ultra-Low-Power Black Phosphorus (B-Ph)/Si Heterojunction Dopingless-Tunnel FET (HD-TFET) with Enhanced Electrical Characteristics

S. Dubey, Kunal Singh, Mirgender Kumar, 2021 .

Effect of Substrate Induced Surface Potential (SISP) on Threshold Voltage of SOI Junction-Less Field Effect Transistor (JLFET)

P. Srinivas, S. Dubey, Rajeev Gupta, 2019, Silicon.

Impact of Temperature Variation on Analog, Hot-Carrier Injection and Linearity Parameters of Nanotube Junctionless Double-Gate-All-Around (NJL-DGAA) MOSFETs

S. Dubey, Himanshi Awasthi, Nitish Kumar, 2021, Silicon.

An Analytical Threshold Voltage Model for Triple-Material Cylindrical Gate-All-Around (TM-CGAA) MOSFETs

Pramod Kumar Tiwari, Abirmoya Santra, Sarvesh Dubey, 2013, IEEE Transactions on Nanotechnology.

Analytical model for subthreshold current and subthreshold swing of short-channel double-material-gate MOSFETs with strained-silicon channel on silicon—germanium substrates

Sarvesh Dubey, Pramod Kumar Tiwari, Gopi Krishna Saramekala, 2014 .

Analytical modeling of subthreshold current and subthreshold swing of Gaussian-doped strained-Si-on-insulator MOSFETs

Sanjay Kumar, S. Jit, S. Dubey, 2014 .