M. Aminpur

Fully-depleted SOI CMOS technology using WXN metal gate and HfSixOyNZ high-k dielectric

O. Faynot, M. Orlowski, T. Skotnicki, 2007, ESSDERC 2007 - 37th European Solid State Device Research Conference.

A novel etch chemistry for low-damage poly-Si gate patterning

M. Aminpur, H. Richter, A. Wolff, 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

A 7nm CMOS technology platform for mobile and high performance compute application

J. Zeng, S. Samavedam, B. Senapati, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Integration of SiCN as a low /spl kappa/ etch stop and Cu passivation in a high performance Cu/low /spl kappa/ interconnect

Ertugrul Demircan, Larry Zhao, Steve Park, 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).