K.A. Bowman

Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance

K.A. Bowman, J.W. Tschanz, Nam Sung Kim, 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

Optimal Repeaters for Sub-50nm Interconnect Networks

K.A. Bowman, J.A. Davis, R. Venkatesan, 2006, 2006 International Interconnect Technology Conference.

Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance

K.A. Bowman, J.W. Tschanz, Nam Sung Kim, 2009, IEEE Journal of Solid-State Circuits.

Microprocessor power optimization through multi-performance device insertion

K.A. Bowman, H.L. Yeager, M.J. Patyra, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

Maximum clock frequency distribution model with practical VLSI design considerations

K.A. Bowman, S.B. Samaan, N.Z. Hakim, 2004, 2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866).