T. Karnik

发表

Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance

K.A. Bowman, J.W. Tschanz, Nam Sung Kim, 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

Hierarchical partitioning of high-level VHDL structures

Sung-Mo Kang, T. Karnik, S. Kang, 1994, Proceedings of VHDL International Users Forum.

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package

S. Narendra, V. De, S. Borkar, 2005, IEEE Journal of Solid-State Circuits.

A Linear Regulator with Fast Digital Control for Biasing Integrated DC-DC Converters

S. Rajapandian, Sung Tae Moon, T. Karnik, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

SRAM dynamic stability estimation using MPFP

Nam-Sung Kim, T. Karnik, D. Khalil, 2007, 2007 Internatonal Conference on Microelectronics.

Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-/spl mu/m to 90-nm generation

J. Tschanz, T. Karnik, P. Hazucha, 2003, IEEE International Electron Devices Meeting 2003.

Optimal Design of Monolithic Integrated DC-DC Converters

T. Karnik, P. Hazucha, G. Schrom, 2006, 2006 IEEE International Conference on IC Design and Technology.

High-level hot carrier reliability-driven synthesis using macro-models

Sung-Mo Kang, Chin-Chi Teng, T. Karnik, 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters

S. Rajapandian, Sung Tae Moon, T. Karnik, 2007, IEEE Journal of Solid-State Circuits.

Effect of Power Supply Noise on SRAM Dynamic Stability

M. Khellah, T. Karnik, Y. Ismail, 2007, 2007 IEEE Symposium on VLSI Circuits.

Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance

K.A. Bowman, J.W. Tschanz, Nam Sung Kim, 2009, IEEE Journal of Solid-State Circuits.

A 233MHz, 80-87% efficient, integrated, 4-phase DC-DC converter in 90nm CMOS

S. Narendra, V. De, T. Karnik, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction

V. De, G. Taylor, Mingwei Huang, 2008, IEEE Journal of Solid-State Circuits.

Statistical design for variation tolerance: key to continued Moore's law

V. De, T. Karnik, S. Borkar, 2004, 2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866).

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process

S. Narendra, V. De, K. Soumyanath, 2004, IEEE Journal of Solid-State Circuits.

High-tension power delivery: operating 0.18 /spl mu/m CMOS digital logic at 5.4V

S. Rajapandian, T. Karnik, P. Hazucha, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

High-voltage power delivery through charge recycling

S. Rajapandian, K.L. Shepard, T. Karnik, 2006, IEEE Journal of Solid-State Circuits.

Design optimizations of a high performance microprocessor using combinations of dual-V/sub T/ allocation and transistor sizing

J. Tschanz, Liqiong Wei, Yibin Ye, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology

Yibin Ye, T. Karnik, V.K. De, 2009, IEEE Journal of Solid-State Circuits.

Area-efficient linear regulator with ultra-fast load regulation

T. Karnik, P. Hazucha, B.A. Bloechel, 2005, IEEE Journal of Solid-State Circuits.

HiSIM: hierarchical interconnect-centric circuit simulator

Jeng-Liang Tsai, Tsung-Hao Chen, T. Karnik, 2004, ICCAD 2004.

A Delay-Locked Loop Synchronization Scheme for High-Frequency Multiphase Hysteretic DC-DC Converters

R. Bashirullah, Pengfei Li, Lin Xue, 2007, IEEE Journal of Solid-State Circuits.

Low power and noise tolerant 20 Gb/s CMOS TIA for short-distance optical interconnect

T. Karnik, F. Paillet, 2003, Southwest Symposium on Mixed-Signal Design, 2003..

PVT-variations and supply-noise tolerant 45nm dense cache arrays with Diffusion-Notch-Free (DNF) 6T SRAM cells and dynamic multi-Vcc circuits

Kevin Zhang, Vivek De, M. Khellah, 2008, 2008 IEEE Symposium on VLSI Circuits.

Integrated On-Chip Inductors With Magnetic Films

G. Schrom, T. Karnik, P. Hazucha, 2006, IEEE Transactions on Magnetics.

Read and write circuit assist techniques for improving Vccmin of dense 6T SRAM cell

T. Karnik, D. Somasekhar, A. Keshavarzi, 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

Selective node engineering for chip-level soft error rate improvement [in CMOS]

S. Vangal, T. Karnik, P. Hazucha, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

Impact of body bias on alpha- and neutron-induced soft error rates of flip-flops

K. Soumyanath, J. Tschanz, T. Karnik, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

An area-efficient, integrated, linear regulator with ultra-fast load regulation

T. Karnik, P. Hazucha, B. Bloechel, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).