Senling Wang

发表

Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation

Hiroshi Takahashi, Senling Wang, Hanan T. Al-Awadhi, 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

Automotive Functional Safety Assurance by POST with Sequential Observation

Hiroshi Takahashi, Senling Wang, Yoshinobu Higami, 2018, IEEE Design & Test.

A Scan-Out Power Reduction Method for Multi-cycle BIST

Kohei Miyase, Seiji Kajihara, Yasuo Sato, 2012, 2012 IEEE 21st Asian Test Symposium.

Feasibility of Machine Learning Algorithm for Test Partitioning

Yoshinobu Higami, Hiroshi Takahashi, Senling Wang, 2019, 2019 34th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC).

Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262

Yoichi Maeda, Hiroshi Takahashi, Yoshinobu Higami, 2018, 2018 IEEE 23rd European Test Symposium (ETS).

Studies on Test Application at Field Test and Low Power Logic-BIST

Senling Wang, 2014 .

A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST

Xiaoqing Wen, Seiji Kajihara, Yasuo Sato, 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

Reduction of Fault Dictionary Size by Optimizing the Order of Test Patterns Application

Kewal K. Saluja, Yoshinobu Higami, Hiroshi Takahashi, 2020, 2020 35th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC).

Testing of Interconnect Defects in Memory Based Reconfigurable Logic Device (MRLD)

Masayuki Sato, Hiroshi Takahashi, Yoshinobu Higami, 2017, 2017 IEEE 26th Asian Test Symposium (ATS).

Scan-Out Power Reduction for Logic BIST

Kohei Miyase, Seiji Kajihara, Yasuo Sato, 2013, IEICE Trans. Inf. Syst..

A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line

Hiroshi Takahashi, Kewal K. Saluja, Yoshinobu Higami, 2017, IEICE Trans. Inf. Syst..

Diagnosis of Delay Faults in the Presence of Clock Delays Considering Hazards

Kewal K. Saluja, Hiroshi Takahashi, Yoshinobu Higami, 2015 .

A Simulated Annealing based Pattern Selection Method to Handle Power Supply Noise for Resistive Open Fault Diagnosis

Hiroshi Takahashi, Yoshinobu Higami, Senling Wang, 2015 .

Aging Monitoring for Memory-based ReconFigurable Logic Device (MRLD)

Yoshinobu Higami, Hiroshi Takahashi, Senling Wang, 2020, 2020 35th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC).

Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip

Hiroshi Takahashi, Seiji Kajihara, Yasuo Sato, 2015, J. Low Power Electron..

Diagnosis of Delay Faults Considering Hazards

Hiroshi Takahashi, Kewal K. Saluja, Yoshinobu Higami, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST

Hiroshi Takahashi, Senling Wang, Hanan T. Al-Awadhi, 2020, IEICE Trans. Inf. Syst..

On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST

Seiji Kajihara, Yasuo Sato, Takaaki Kato, 2018, 2018 IEEE 27th Asian Test Symposium (ATS).

Trends in 3D Integrated Circuit (3D-IC) Testing Technology

Shyue-Kung Lu, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2015 .

A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips

Xiaoqing Wen, Seiji Kajihara, Yasuo Sato, 2020, IEEE Transactions on Emerging Topics in Computing.

Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays

Kewal K. Saluja, Yoshinobu Higami, Shin-ya Kobayashi, 2016, IPSJ Trans. Syst. LSI Des. Methodol..

Low Power BIST for Scan-Shift and Capture Power

Kohei Miyase, Seiji Kajihara, Yasuo Sato, 2012, 2012 IEEE 21st Asian Test Symposium.

Genetic algorithm based approach for segmented testing

Sudhakar M. Reddy, Seiji Kajihara, Yasuo Sato, 2011, 2011 IEEE/IFIP 41st International Conference on Dependable Systems and Networks Workshops (DSN-W).

Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST

Yoichi Maeda, Hiroshi Takahashi, Yoshinobu Higami, 2018, 2018 IEEE 27th Asian Test Symposium (ATS).

Method for Inserting Fault-Detection-Strengthened Test Point under Multi-cycle Testing

Takahashi Hiroshi, Yoshinobu Higami, Matsushima Jun, 2020 .

Compact Dictionaries for Reducing Compute Time in Adaptive Diagnosis

Kewal K. Saluja, Yoshinobu Higami, Hiroshi Takahashi, 2019, 2019 34th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC).