G. C. Patil

发表

Comparative study of Ge pMOS and In0.3Ga0.7As nMOS with Si MOSFETs for digital applications

S. R. Aher, H. S. Borse, A. V. Jawake, 2015, 2015 Annual IEEE India Conference (INDICON).

A simple analytical model of 4H-SiC MOSFET for high temperature circuit simulations

S. C. Wagaj, G. C. Patil, P. M. Ghate, 2014, 2014 Annual IEEE India Conference (INDICON).

Engineering substrate doping in bulk planar junctionless transistor: Scalability and variability study

G. C. Patil, K. B. Bhagat, 2020, Engineering Research Express.

Analytical model for 4H-SiC superjunction drift layer with anisotropic properties for ultrahigh-voltage applications

P. Kondekar, R. Patrikar, G. C. Patil, 2017 .

A Novel Dual-K Spacer Double Gate Junctionless Transistor for Digital Integrated Circuits

S. R. Aher, H. S. Borse, A. V. Jawake, 2015 .

Performance Analysis of Feedback Field-Effect Transistor-Based Biosensor

G. C. Patil, Deepika Singh, 2020, IEEE Sensors Journal.

Si3N4: HfO2 dual-k spacer dopant-segregated Schottky barrier SOI MOSFET for low-power applications

S. Qureshi, G. C. Patil, 2011, 2011 IEEE International Conference of Electron Devices and Solid-State Circuits.

Integrated computational approach towards identification of HSPG and ACE2 mimicking moieties for SARS-CoV-2 inhibition

G. C. Patil, A. Kuthe, Satyendra Chandra Tripathi, 2022, Journal of Molecular Liquids.

Underlap channel silicon-on-insulator quantum dot floating-gate MOSFET for low-power memory applications

G. C. Patil, Chetan T. Dabhi, 2016 .

Analytical model for 4H-SiC superjunction drift layer with anisotropic properties for ultrahigh-voltage applications

P. Kondekar, R. Patrikar, G. C. Patil, 2017, Journal of Computational Electronics.

Comparative analysis of GaN-on-3CSiC and conventional Si MOSFET for digital integrated circuits

H. S. Borse, A. V. Jawake, K. Bhosale, 2015, 2015 Annual IEEE India Conference (INDICON).

Buried Metal Silicon-on-Insulator Junctionless Transistor for Low Power CMOS Logic Circuits

G. C. Patil, Kaustubh K. Tiple, 2022, Silicon.

Underlap channel silicon-on-insulator quantum dot floating-gate MOSFET for low-power memory applications

G. C. Patil, Chetan T. Dabhi, 2016, Journal of Computational Electronics.

Thermal stability analysis of buffered layer P3HT/P3HT:PCBM organic solar cells

Ishan C. Ghosekar, G. C. Patil, 2019, IET Optoelectronics.

Engineering spacers in dopant-segregated Schottky barrier SOI MOSFET for nanoscale CMOS logic circuits

S. Qureshi, G. C. Patil, 2012 .

Fabrication and characterization of lead sulfide and multi-walled carbon nanotube based field effect transistors using low cost chemical route

G. C. Patil, B. Sankapal, S. T. Ingle, 2021, Engineering Research Express.

Investigation of transport in edge passivated armchair silicene nanoribbon field effect transistor by ab-initio based Wannierised tight binding

G. C. Patil, R. Junghare, 2021 .

Buried Metal Silicon-on-Insulator Junctionless Transistor for Low Power CMOS Logic Circuits

G. C. Patil, Kaustubh K. Tiple, 2022, Silicon.

Asymmetric Drain Underlap Schottky Barrier SOI MOSFET for Low-Power High Performance Nanoscale CMOS Circuits

S. Qureshi, Ganesh C. Patil, S. Qureshi, 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

Negative capacitance δ ‐bulk planar junctionless transistor for low power applications

G. C. Patil, K. B. Bhagat, 2019, Micro & Nano Letters.

Si3N4: HfO2 dual-k spacer bulk planar junctionless transistor for mixed signal integrated circuits

Ganesh C. Patil, Ramarao Garike, G. C. Patil, 2018, IET Circuits Devices Syst..

Novel δ-doped partially insulated junctionless transistor for mixed signal integrated circuits

G. C. Patil, Vijaysinh H. Bonge, M. Malode, 2016 .

Underlap channel metal source/drain SOI MOSFET for thermally efficient low-power mixed-signal circuits

S. Qureshi, Ganesh C. Patil, S. Qureshi, 2012, Microelectron. J..

Dielectric-Modulated Bulk-Planar Junctionless Field-Effect Transistor for Biosensing Applications

G. C. Patil, Deepika Singh, 2021, IEEE Transactions on Electron Devices.

Investigation of structural, electronic and transport properties of Silicene on Graphene heterostructure by ab-initio calculations

Gopal S. Pranjale, G. C. Patil, R. Junghare, 2022, 2022 IEEE International Conference on Emerging Electronics (ICEE).

Review on performance analysis of P3HT:PCBM-based bulk heterojunction organic solar cells

Ishan C. Ghosekar, G. C. Patil, 2021 .

Impact of concentration variation and thermal annealing on performance of multilayer OSC consisting of sandwiched P3HT layer between PEDOT:PSS and P3HT:PCBM

Ishan C. Ghosekar, G. C. Patil, 2020 .

Performance Analysis and Thermal Reliability Study of Multilayer Organic Solar Cells

Ishan C. Ghosekar, G. C. Patil, 2019, IEEE Transactions on Device and Materials Reliability.

Improving organic solar cell efficiency using solution processed poly (3‐hexylthiophene) buffer layer

Ishan C. Ghosekar, G. C. Patil, 2019, Micro & Nano Letters.

Optimizing device efficiency of P3HT/P3HT:PCBM interlayer organic solar cell: Annealing dependent study

Ishan C. Ghosekar, G. C. Patil, 2018, 2018 4th IEEE International Conference on Emerging Electronics (ICEE).

Fabrication of Ag2S, Bi2S3 and CdS p-FETs using Solution Processing

Gopal S. Pranjale, G. C. Patil, S. T. Ingle, 2022, 2022 IEEE International Conference on Emerging Electronics (ICEE).

Engineering buried oxide in dopant-segregated Schottky barrier SOI MOSFET for nanoscale CMOS circuits

S. Qureshi, Ganesh C. Patil, S. Qureshi, 2013, Microelectron. Reliab..

Asymmetric drain underlap dopant-segregated Schottky barrier ultrathin-body SOI MOSFET for low-power mixed-signal circuits

S. Qureshi, G. C. Patil, 2013 .