A. Milenin

发表

Investigation of the impact of plasma etching steps on the roughness of the fin FET channel sidewalls in the scheme of hetero-integration

G. Baranov, A. Milenin, M. Baklanov, 2016 .

Study on metrology of ERU tuning in TCP reactor, using PVx2 sensor wafer

H. Struyf, A. Milenin, W. Boullart, 2010, 2010 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC).

First demonstration of ferroelectric Si:HfO2 based 3D FE-FET with trench architecture for dense nonvolatile memory application

J. V. Houdt, J. van Houdt, A. Milenin, 2021, 2021 IEEE International Memory Workshop (IMW).

First Demonstration of Vertically Stacked Gate-All-Around Highly Strained Germanium Nanowire pFETs

A. Hikavyy, K. Wostyn, H. Bender, 2018, IEEE Transactions on Electron Devices.

First demonstration of strained Ge-in-STI IFQW pFETs featuring raised SiGe75% S/D, replacement metal gate and germanided local interconnects

A. Hikavyy, H. Bender, A. Thean, 2013, 2013 Symposium on VLSI Circuits.

Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

L. Witters, N. Waldron, D. Mocuta, 2017, IEEE Transactions on Electron Devices.

Seedless Templated Growth of Hetero-Nanostructures for Novel Microelectronics Devices

H. Bender, F. Iacopi, R. Loo, 2009 .

EELS peak intensity dependence on primary electron energy for the Si(111)7×7 and Si(111)-Cr surface structures

A. Milenin, N. Plusnin, V. Soldatov, 1999 .

Self-aligned double patterning process for subtractive Ge fin fabrication at 45-nm pitch

K. Barla, A. Thean, L. Witters, 2016 .

Advanced CMOS manufacturing, a drive for plasma science and technology

Werner Boullart, Efrain Altamirano Sanchez, Jean-Francois de Marneffe, 2012 .

Ordered silicon nanostructures by ion beam induced glancing angle deposition

A. Milenin, C. Patzig, B. Rauschenbach, 2007 .

An In-depth Study of High-Performing Strained Germanium Nanowires pFETs

H. Mertens, R. Ritzenthaler, A. Hikavyy, 2018, 2018 IEEE Symposium on VLSI Technology.

Transfer of Sub-30-nm Patterns from Templates Based on Supramolecular Assemblies

M. Steinhart, U. Gösele, R. Scholz, 2007 .

Relaxation of strain in patterned strained silicon investigated by UV Raman spectroscopy

M. Reiche, U. Gösele, I. Radu, 2006 .

Strain relaxation in nanopatterned strained silicon round pillars

M. Reiche, U. Gösele, I. Radu, 2007 .

Understanding the factors affecting contact resistance in nanowire field effect transistors (NWFETs) to improve nanoscale contacts for future scaling

H. Bender, N. Collaert, T. Ivanov, 2022, Journal of Applied Physics.

(Invited) Selective Etch of Si and SiGe for Gate All-Around Device Architecture

Naoto Horiguchi, Liesbeth Witters, Aaron Thean, 2015 .

Visible range whispering-gallery mode in microdisk array based on size-controlled Si nanocrystals

U. Gösele, Rongjun Zhang, M. Zacharias, 2006 .

First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs

A. Hikavyy, K. Wostyn, H. Bender, 2018, 2018 IEEE Symposium on VLSI Technology.

Formation of the Co/Si(111)7×7 interface: AES- and EELS-study

A. Milenin, N. Plusnin, D. P. Prihod'ko, 2000 .

A dc-pulsed capacitively coupled planar Langmuir probe for plasma process diagnostics and monitoring

A. Milenin, W. Boullart, J. Booth, 2012 .

Study on processing step uniformity tuning during FET fabrication and sensor wafer response as a function of chuck temperature adjustment

A. Milenin, W. Boullart, Y. Wen, 2014 .

C2H4-Based Plasma-Assisted CD Shrink and Contact Patterning for RRAM Application

N. Jossart, M. Jurczak, J. Lisoni, 2010 .

Top-down InGaAs nanowire and fin vertical FETs with record performance

H. Bender, A. Thean, N. Collaert, 2016, 2016 IEEE Symposium on VLSI Technology.

Plasma etching of proton-exchanged lithium niobate

Huiying Hu, W. Sohler, R. Wehrspohn, 2006 .

A Low-Power HKMG CMOS Platform Compatible With Dram Node 2× and Beyond

Naoto Horiguchi, Wilfried Vandervorst, Tom Schram, 2014, IEEE Transactions on Electron Devices.

Low-loss, low-temperature PVD SiN waveguides

P. Verheyen, T. Witters, J. de Coster, 2021, International Conference on Group IV Photonics.

Advanced 300-mm waferscale patterning for silicon photonics devices with record low loss and phase errors

Shankar Kumar Selvaraja, Wim Bogaerts, Joris Van Campenhout, 2012 .

SOI planar photonic crystal fabrication: Etching through SiO2/Si/SiO2 layer systems using fluorocarbon plasmas

U. Gösele, R. Wehrspohn, A. Milenin, 2005 .

Temperature and RF Current Sensor Wafers for Plasma Etching

M. Demand, A. Milenin, W. Boullart, 2011 .

15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

A. Brand, P. Eyben, L. Witters, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

The SERS and TERS effects obtained by gold droplets on top of Si nanowires.

J. Michler, P. Werner, A. Milenin, 2007, Nano letters.

High-temperature resistant, ordered gold nanoparticle arrays

Dong Ha Kim, M. Steinhart, C. Hawker, 2006 .

Influence of the Top Chamber Window Temperature on the STI Etch Process

D. Shamiryan, A. Milenin, S. Tinck, 2010 .

The SOI planar photonic crystal fabrication: patterning of Cr using Cl2/O2 plasma etching

M. Reiche, R. Wehrspohn, A. Milenin, 2005 .

Ordered arrays of <100>-oriented silicon nanorods by CMOS-compatible block copolymer lithography.

Dong Ha Kim, M. Steinhart, C. Hawker, 2007, Nano letters.

Silicon-based low-loss photonic crystal waveguides

Ralf B. Wehrspohn, Daniel Pergande, Andreas von Rhein, 2007, SPIE OPTO.

Investigation of the impact of plasma etching steps on the roughness of the fin FET channel sidewalls in the scheme of hetero-integration

G. Baranov, A. Milenin, M. Baklanov, 2016, Russian Microelectronics.

An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates

C. Merckling, D. Lin, N. Waldron, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Record 47 mV/dec top-down vertical nanowire InGaAs/GaAsSb tunnel FETs

Nadine Collaert, Tsvetan Ivanov, Dennis Lin, 2018, 2018 IEEE Symposium on VLSI Technology.

Record performance Top-down In0.53Ga0.47As vertical nanowire FETs and vertical nanosheets

N. Collaert, A. Veloso, T. Ivanov, 2017, International Electron Devices Meeting.

Fabrication challenges and opportunities for high-mobility materials: from CMOS applications to emerging derivative technologies

A. Vais, N. Collaert, N. Horiguchi, 2019, Advanced Lithography.

(Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs

Geert Hellings, Eddy Simoen, Niamh Waldron, 2017 .

N7 FinFET Self-Aligned Quadruple Patterning Modeling

T. Schram, A. Milenin, S. Baudot, 2018, 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

Patterning challenges in advanced device architectures: FinFETs to nanowires

L. Witters, N. Waldron, N. Collaert, 2016, SPIE Advanced Lithography.

Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

L. Witters, D. Mocuta, N. Collaert, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Strained Germanium quantum well pMOS FinFETs fabricated on in situ phosphorus-doped SiGe strain relaxed buffer layers using a replacement Fin process

L. Witters, N. Waldron, N. Collaert, 2013, 2013 IEEE International Electron Devices Meeting.

First demonstration of 15nm-WFIN inversion-mode relaxed-Germanium n-FinFETs with Si-cap free RMG and NiSiGe Source/Drain

H. Mertens, A. Hikavyy, H. Bender, 2014, 2014 IEEE International Electron Devices Meeting.

Wafer‐Scale Integration of Single Layer Graphene Electro‐Absorption Modulators in a 300 mm CMOS Pilot Line

K. Vandersmissen, C. Huyghebaert, A. Centeno, 2023, Laser & Photonics Reviews.

Wafer-scale graphene electro-absorption modulators fabricated in a 300 mm CMOS platform

K. Vandersmissen, C. Huyghebaert, A. Centeno, 2023, Photonex.

Graphene electro-absorption modulators integrated at wafer-scale in a CMOS fab

Cedric Huyghebaert, Joris Van Campenhout, Marianna Pantouvaki, 2021, 2021 Symposium on VLSI Circuits.