B. Majkusiak

发表

Comparison of advanced transport models for nanoscale nMOSFETs

G. Baccarani, A. Asenov, L. Selmi, 2009, 2009 10th International Conference on Ultimate Integration of Silicon.

The remote roughness mobility resulting from the ultrathin SiO2 thickness nonuniformity in the DG SOI and bulk MOS transistors

B. Majkusiak, J. Walczak, 2001 .

Analysis of the MOS transistor based on the self-consistent solution to the Schrodinger and Poisson equations and on the local mobility model

B. Majkusiak, T. Janik, 1998 .

Drain current computation in nanoscale nMOSFETs: Comparison of transport models

G. Baccarani, A. Asenov, L. Selmi, 2010, 2010 27th International Conference on Microelectronics Proceedings.

Influence of oxide thickness nonuniformities on the tunnel current‐voltage and capacitance‐voltage characteristics of the metal‐oxide‐semiconductor system

B. Majkusiak, A. Strojwas, 1993 .

Very thin oxides in vlsi technology: Properties and device implications

B. Majkusiak, A. Jakubowski, 1990 .

Effect of traps-to-gate tunnel communication on C-V characteristics of MIS capacitors

B. Majkusiak, A. Mazurak, J. Jasiński, 2019, Microelectronic Engineering.

Semiconductor thickness effects in the double-gate SOI MOSFET

Bogdan Majkusiak, B. Majkusiak, J. Walczak, 1998 .

Simulation of the gate tunnel current in the double gate (DG) MOS transistor

B. Majkusiak, J. Walczak, B. Majkusiak, 2006 .

Technology and characterization of MIS structures with co-doped silicon nanocrystals (Si-NCs) embedded in hafnium oxide (HfOx) ultra-thin layers

J. Valenta, H. Sugimoto, M. Fujii, 2017 .

A technical formula for determining the insulator capacitance in a MOS structure

B. Majkusiak, A. Jakubowski, 1992 .

Comparison of gate leakage current components in metal-insulator-semiconductor structures with high-k gate dielectris

B. Majkusiak, T. Janik, A. Jakubowski, 2001 .

Simulations of transient processes and characteristics of the nc-MOS structures

B. Majkusiak, A. Mazurak, D. Tanous, 2017 .

Modeling the Tunnel Field-Effect Transistor Based on Different Tunneling Path Approaches

B. Majkusiak, P. Wiśniewski, 2018, IEEE Transactions on Electron Devices.

Theoretical Limit for the SiO2 Thickness in Silicon MOS Devices

B. Majkusiak, J. Walczak, 2005 .

WKB approximation based formula for tunneling probability through a multi-layer potential barrier

B. Majkusiak, A. Mazurak, 2012, 2012 15th International Workshop on Computational Electronics.

Modeling the Current–Voltage Characteristics of Ge₁₋ₓSnₓ Electron–Hole Bilayer TFET With Various Compositions

B. Majkusiak, P. Wiśniewski, 2020, IEEE Transactions on Electron Devices.

The initial growth rate of thermal silicon oxide

B. Majkusiak, R. B. Beck, 1989 .

Transport and quantum scattering time in field-effect transistors

J. Łusakowski, B. Majkusiak, M. Sakowicz, 2007 .

Modeling and Simulation Approaches for Gate Current Computation

M. Luisier, A. Spinelli, P. Palestri, 2013 .

Series resistance in a MOS capacitor with a thin gate oxide

Krzysztof Iniewski, B. Majkusiak, A. Jakubowski, 1989 .

Switching mechanism in MIS (n‐p) devices

B. Majkusiak, A. Jakubowski, J. Ruzylslso, 1980 .

On electron tunneling in the metal-insulator-semiconductor systems including various electron effective masses

Bogdan Majkusiak, A. Jakubowski, B. Majkusiak, 1985 .

Charging/discharging processes in nanocrystaline MOS structures - Theoretical study

Bogdan Majkusiak, Andrzej Mazurak, Dominik Tanous, 2016 .

Resonant Tunneling Devices on SOI Basis

B. Majkusiak, 2007 .

Gate tunnel current in an MOS transistors

B. Majkusiak, B. Majkusiak, 1990 .

Small-signal admittance model as a characterization tool of the MOS tunnel diode

B. Majkusiak, J. Jasiński, 2013 .

Modeling of tunnel field effect transistor: the impact of construction parameters

Bogdan Majkusiak, Piotr Wiśniewski, B. Majkusiak, 2016, Electron Technology Conference.

Influence of carrier energy quantization on the gate-induced drain breakdown

B. Majkusiak, T. Janik, 1995 .

Comparison of Modeling Approaches for the Capacitance–Voltage and Current–Voltage Characteristics of Advanced Gate Stacks

C. Busseret, E. Langer, C. Fiegna, 2007, IEEE Transactions on Electron Devices.

Effect of interface traps parameters on admittance characteristics of the MIS (metal-insulator-semiconductor) tunnel structures

Jakub Jasiński, Bogdan Majkusiak, Andrzej Mazurak, 2016, Electron Technology Conference.

Small-signal admittance model of multi-traps distributed over energy and space in the insulator of MIS tunnel structures

B. Majkusiak, A. Mazurak, J. Jasiński, 2015 .

Study of the effect of tunneling through the traps inside the insulator on small-signal admittance of the MOS structure

B. Majkusiak, A. Mazurak, J. Jasiński, 2013 .

Effect of inner interface traps on high-k gate stack admittance characteristics

B. Majkusiak, A. Mazurak, J. Jasiński, 2016, 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

Modeling the Inelastic Scattering Effect on the Resonant Tunneling Current

B. Majkusiak, 2007 .

Theoretical Study of Electron Mobility in Double-Gate Field Effect Transistors with Multilayer (strained-)Si/SiGe Channel

B. Majkusiak, J. Walczak, 2008 .

Investigation of Electrical Properties of the Al/SiO2/n++-Si Resistive Switching Structures by Means of Static, Admittance, and Impedance Spectroscopy Measurements

B. Majkusiak, A. Mazurak, J. Jasiński, 2021, Materials.

Scattering mechanisms in MOS/SOI devices with ultrathin semiconductor layers

B. Majkusiak, J. Walczak, 2004, Journal of Telecommunications and Information Technology.

Quantum-mechanical effects in SOI devices

B. Majkusiak, 2001 .

Electron energy quantization effects in the very thin film GAA SOI transistor

B. Majkusiak, T. Janik, 1997 .

Influence of carrier energy quantization on threshold voltage of metal‐oxide‐semiconductor transistor

Bogdan Majkusiak, B. Majkusiak, T. Janik, 1994 .