Philippe Maurine

发表

Injection of transient faults using electromagnetic pulses -Practical results on a cryptographic system-

Amine Dehbaoui, Jean-Max Dutertre, Bruno Robisson, 2012, IACR Cryptol. ePrint Arch..

Electromagnetic Attacks on Ring Oscillator-Based True Random Number Generator

Bruno Robisson, Philippe Maurine, Lilian Bossuet, 2012 .

Efficiency of the RDVFS countermeasure

Philippe Maurine, Sebastien Ordas, Mathieu Carbone, 2014, 2014 IEEE Faible Tension Faible Consommation.

Collision Based Attacks in Practice

Philippe Maurine, Ibrahima Diop, Pierre-Yvan Liardet, 2015, 2015 Euromicro Conference on Digital System Design.

Request-skip adders : CMOS standard cell data dependent adders

Philippe Maurine, Robin Perrot, Nadine Azemard, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

Implementation and efficiency evaluation of construction-based countermeasures against electromagnetic analysis

Amine Dehbaoui, Philippe Maurine, Michel Robert, 2011, 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Structure Independent Representation of Output Transition Time for CMOS Library

Philippe Maurine, Daniel Auvergne, Nadine Azémard, 2002, PATMOS.

A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks

Lionel Torres, Amine Dehbaoui, Philippe Maurine, 2010, SBCCI '10.

Evaluation oftherobustness ofdualrail logic against DPA

Philippe Maurine, M. Robert, Alin Razafindraibe, 2006 .

Editorial

Johan Vounckx, Philippe Maurine, Nadine Azémard, 2008, Integr..

Interest of MIA in frequency domain?

Philippe Maurine, Mathieu Carbone, Yannick Teglia, 2015, CS2@HiPEAC.

Embedding statistical tests for on-chip dynamic voltage and temperature monitoring

Philippe Maurine, Edith Beigné, Suzanne Lesecq, 2012, DAC Design Automation Conference 2012.

Temperature and Fast Voltage On-Chip Monitoring using Low-Cost Digital Sensors

Philippe Maurine, Julien Mottin, Edith Beigne, 2013 .

Body Biasing Injection Attacks in Practice

Jean-Max Dutertre, Philippe Maurine, Jean-Baptiste Rigaud, 2016, CS2@HiPEAC.

EM Injection: Fault Model and Locality

Philippe Maurine, Sébastien Ordas, Ludovic Guillaume-Sage, 2015, 2015 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC).

Modeling Time Domain Magnetic Emissions of ICs

Lionel Torres, Philippe Maurine, Mathieu Lisart, 2010, PATMOS.

Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks

Philippe Maurine, Michel Robert, Alin Razafindraibe, 2006, PATMOS.

Analysis Of Variance and CPA in SCA

Philippe Maurine, Driss Aboulkassimi, Mathieu Carbone, 2014, IACR Cryptol. ePrint Arch..

Transition time modeling in deep submicron CMOS

Philippe Maurine, Daniel Auvergne, Nadine Azémard, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Electromagnetic Analysis Perturbation using Chaos Generator

Romain Wacquez, Philippe Maurine, J. Postel-Pellerin, 2016 .

Assessment of the Immunity of Unshielded Multi-Core Integrated Circuits to Near-Field Injection

Philippe Maurine, Lionel Torres, Richard Perdriau, 2009, 2009 20th International Zurich Symposium on Electromagnetic Compatibility.

A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM

Philippe Maurine, Michel Robert, Magali Bastian, 2008, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008).

A Secure D Flip-Flop against Side Channel Attacks

Philippe Maurine, Sébastien Tiran, Bruno Vaquie, 2011, PATMOS.

SSTA Considering Effects of Structure Correlations, Input Slope and Output Load Variations

Philippe Maurine, Nadine Azemard, Zeqin Wu, 2008 .

Electromagnetic analyses of secure circuits: Results on FPGA & ASIC

Philippe Maurine, 2009 .

Performance Metric Based Optimization Protocol

Philippe Maurine, Daniel Auvergne, Nadine Azémard, 2004, PATMOS.

Importance of IR drops on the modeling of laser-induced transient faults

Jean-Max Dutertre, Philippe Maurine, Rodrigo Possamai Bastos, 2017, 2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

Evaluation on FPGA of triple rail logic robustness against DPA and DEMA

Lionel Torres, Philippe Maurine, Michel Robert, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

An Embedded Digital Sensor against EM and BB Fault Injection

Philippe Maurine, Jean-Baptiste Rigaud, David El-Baze, 2016, 2016 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC).

A fully-digital EM pulse detector

Philippe Maurine, Jean-Baptiste Rigaud, David El-Baze, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects

Robin Wilson, Philippe Maurine, Sylvain Engels, 2006, Integr..

Circuit Sizing Methodunder DelayConstraint

Philippe Maurine, Nadine Azemard, Alexandre Verle, 2006 .

Thoroughly analyzing the use of ring oscillators for on-chip hardware trojan detection

Philippe Maurine, Jacques J. A. Fournier, Maxime Lecomte, 2015, 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

Voltage Spikes on the Substrate to Obtain Timing Faults

Philippe Maurine, Pierre-Yvan Liardet, Mathieu Lisart, 2013, 2013 Euromicro Conference on Digital System Design.

Gate speed improvement at minimal power dissipation

Philippe Maurine, Daniel Auvergne, Nadine Azémard, 2002, Asia-Pacific Conference on Circuits and Systems.

Spatial EM jamming: A countermeasure against EM Analysis?

Pascal Benoit, Lionel Torres, Philippe Maurine, 2010, 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip.

Chapter 2 Security FPGA Analysis

Jean-Luc Danger, Pascal Benoit, Lionel Torres, 2011 .

Product On-Chip Process Compensation for Low Power and Yield Enhancement

Robin Wilson, Philippe Maurine, David Meyer, 2009, PATMOS.

Estimating the Signal-to-Noise Ratio Under Repeated Sampling of the Same Centered Signal: Applications to Side-Channel Attacks on a Cryptoprocessor

Philippe Maurine, Gilles R. Ducharme, P. Maurine, 2018, IEEE Transactions on Information Theory.

Leakage Assessment Through Neural Estimation of the Mutual Information

Philippe Maurine, Maxime Lecomte, Valence Cristiani, 2020, ACNS Workshops.

SSTA considering switching process induced correlations

Philippe Maurine, Nadine Azémard, Gilles R. Ducharme, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

Optimization Protocol Based on Performance Metric

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2004 .

Physical Extension of the Logical Effort Model

Robin Wilson, Philippe Maurine, Daniel Auvergne, 2004, PATMOS.

Statistical Lock-in Thermography to Improve Contrast and Detectivity of ICs Thermal Maps

Philippe Maurine, Jean-Marc Galliere, Maxime Cozzi, 2019, 2019 25th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC).

Statistical Characterization of Library Timing Performance

Robin Wilson, Philippe Maurine, Sylvain Engels, 2006, PATMOS.

Standard CAD Tool-Based Method for Simulation of Laser-Induced Faults in Large-Scale Circuits

Jean-Max Dutertre, Philippe Maurine, Rodrigo Possamai Bastos, 2018, ISPD.

Thermal Scans for Detecting Hardware Trojans

Philippe Maurine, Jean Marc Gallière, Maxime Cozzi, 2018, COSADE.

Timing Performance Representation of a CMOS Standard Cell Library

Philippe Maurine, Daniel Auvergne, Sylvain Engels, 2003 .

Breaking Mobile Firmware Encryption through Near-Field Side-Channel Analysis

Philippe Maurine, Aurélien Vasselle, Maxime Cozzi, 2019, ASHES@CCS.

Evidence of a Larger EM-Induced Fault Model

Jean-Max Dutertre, Philippe Maurine, Sébastien Ordas, 2014, CARDIS.

On-chip fingerprinting of IC topology for integrity verification

Philippe Maurine, Jacques J. A. Fournier, Maxime Lecomte, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Timing margin evaluation with a simple statistical timing analysis flow

Robin Wilson, Philippe Maurine, Sylvain Engels, 2009, J. Embed. Comput..

Finding EM leakages at design stage: a simulation methodology

Philippe Maurine, Alexandre Sarafianos, Davide Poggi, 2020, IACR Cryptol. ePrint Arch..

Deep Submicron Switching Current Modeling for CMOS Logic Output Transition Time Determination

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2001 .

SECNUM: an Open Characterizing Platform for Integrated Circuits

Pascal Benoit, Lionel Torres, Philippe Maurine, 2012 .

On Adaptive Bandwidth Selection for Efficient MIA

Philippe Maurine, Mathieu Carbone, Yannick Teglia, 2014, COSADE.

Compact and Secured Primitives for the Design of Asynchronous Circuits

Philippe Maurine, Michel Robert, Alin Razafindraibe, 2005, J. Low Power Electron..

Perfornance Evaluation for Submicron CMOS Design

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2001 .

An On-Chip Technique to Detect Hardware Trojans and Assist Counterfeit Identification

Philippe Maurine, Maxime Lecomte, Jacques Fournier, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Second Generation Delay Model for Submicron CMOS Process

Philippe Maurine, Daniel Auvergne, Mustapha Rezzoug, 2000, PATMOS.

Temperature Dependence in Low Power CMOS UDSM Process

Robin Wilson, Philippe Maurine, Daniel Auvergne, 2004, PATMOS.

Local Condition Monitoring in integrated circuits using a set of Kolmogorov-Smirnov tests

Philippe Maurine, Edith Beigné, Suzanne Lesecq, 2012, 2012 IEEE International Conference on Control Applications.

Circuit optimization based on speed indicators

Philippe Maurine, Nadine Azémard, Alexandre Verle, 2005, 2005 12th IEEE International Conference on Electronics, Circuits and Systems.

Techniques for EM Fault Injection: Equipments and Experimental Results

Philippe Maurine, 2012, 2012 Workshop on Fault Diagnosis and Tolerance in Cryptography.

Improvement of dual rail logic as a countermeasure against DPA

Philippe Maurine, Michel Robert, Alin Razafindraibe, 2007, 2007 IFIP International Conference on Very Large Scale Integration.

Amplitude demodulation-based EM analysis of different RSA implementations

Pascal Benoit, Lionel Torres, Philippe Maurine, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Variabilité de Process et Performances des Mémoires SRAM Embarquées

Philippe Maurine, Michel Robert, Magali Bastian Hage-Hassan, 2007 .

Metric Definition for Buffer Insertion

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2002 .

The Impact of Pulsed Electromagnetic Fault Injection on True Random Number Generators

Ingrid Verbauwhede, Philippe Maurine, Dave Singelée, 2018, 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC).

Temperature- and Voltage-Aware Timing Analysis

Robin Wilson, Philippe Maurine, Nadine Azémard, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

General representation of CMOS structure transition time for timing library representation

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2002 .

Enhancing electromagnetic attacks using spectral coherence based cartography

Lionel Torres, Amine Dehbaoui, Philippe Maurine, 2009, 2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC).

On the use of the EM medium as a fault injection means

Jean-Max Dutertre, Bruno Robisson, Philippe Maurine, 2012 .

SCA with Magnitude Squared Coherence

Philippe Maurine, Sébastien Tiran, P. Maurine, 2012, CARDIS.

Integration, the VLSI Journal

Johan Vounckx, Philippe Maurine, Nadine Azemard, 2008 .

Practical Analysis of RSA Countermeasures Against Side-Channel Electromagnetic Attacks

Laurent Imbert, Lionel Torres, Philippe Maurine, 2013, CARDIS.

Yet Another Fault Injection Technique : by Forward Body Biasing Injection

Philippe Maurine, Pierre Yvan Liardet, Thomas Ordas, 2012 .

Interpreting SSTA Results with Correlation

Philippe Maurine, Nadine Azémard, Gilles R. Ducharme, 2009, PATMOS.

Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design

Philippe Maurine, Daniel Auvergne, Mustapha Rezzoug, 2000, PATMOS.

Conditional Moments based SSTA Considering Switching Process Induced Correlations

Philippe Maurine, Nadine Azemard, Zeqin Wu, 2008 .

Design Optimization with Automated Cell Generation

Philippe Maurine, Michel Robert, Daniel Auvergne, 2004, PATMOS.

A frequency leakage model for SCA

Philippe Maurine, Yannick Teglia, Michel Agoyan, 2014, 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

From theory to practice: horizontal attacks on protected implementations of modular exponentiations

Philippe Maurine, Ibrahima Diop, Pierre-Yvan Liardet, 2018, Journal of Cryptographic Engineering.

Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization

Christian Bernard, Philippe Maurine, Edith Beigné, 2011, Microelectron. J..

Method for evaluation of transient-fault detection techniques

Jean-Max Dutertre, Philippe Maurine, Rodrigo Possamai Bastos, 2017, Microelectron. Reliab..

Delay bound based CMOS gate sizing technique

Philippe Maurine, Daniel Auvergne, Nadine Azémard, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Feasible Delay Bound Definition

Philippe Maurine, Daniel Auvergne, Nadine Azémard, 2001, VLSI-SOC.

Automatic Layout Synthesis Based Performance Optimization

Philippe Maurine, Michel Robert, Daniel Auvergne, 2004 .

Technological countermeasures for IC protection against EM Analysis

Philippe Maurine, Mathieu Lisart, Thomas Ordas, 2009 .

Side Channel Attacks

Michel Robert, Lionel Torres, Philippe Maurine, 2011 .

A model of the leakage in the frequency domain and its application to CPA and DPA

Philippe Maurine, Yannick Teglia, Michel Agoyan, 2014, Journal of Cryptographic Engineering.

Low power oriented CMOS circuit optimization protocol

Philippe Maurine, Daniel Auvergne, Nadine Azémard, 2005, Design, Automation and Test in Europe.

Security FPGA Analysis

Pascal Benoit, Lionel Torres, Philippe Maurine, 2011 .

Technological Assignment for a Minimal Power Consumption

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2001 .

On-Chip Process Variability Monitoring

Philippe Maurine, Sylvain Engels, Robin Wilson, 2009 .

Timing analysis in presence of supply voltage and temperature variations

Robin Wilson, Philippe Maurine, Nadine Azémard, 2006, ISPD '06.

A New Process Characterization Method for FPGAs Based on Electromagnetic Analysis

Pascal Benoit, Lionel Torres, Philippe Maurine, 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

Gate Sizing for Low Power Design

Philippe Maurine, Daniel Auvergne, Nadine Azémard, 2001, VLSI-SOC.

Dynamic Variability Monitoring Using Statistical Tests for Energy Efficient Adaptive Architectures

Philippe Maurine, Edith Beigné, Julien Mottin, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

Ripple Carry Adder for Micropipeline Circuits

Philippe Maurine, Robin Perrot, Nadine Azemard, 2005 .

Vertical and horizontal correlation attacks on RNS-based exponentiations

Laurent Imbert, Lionel Torres, Philippe Maurine, 2015, Journal of Cryptographic Engineering.

Extraction of intrinsic structure for Hardware Trojan detection

Philippe Maurine, Jacques J. A. Fournier, Maxime Lecomte, 2015, IACR Cryptol. ePrint Arch..

Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits

Lionel Torres, Philippe Maurine, Mathieu Lisart, 2008, PATMOS.

A Simulation Flow for Time Domain Magnetic Radiations of ICs

Philippe Maurine, Lionel Torres, Mathieu Lisart, 2010 .

An evaluation of an AES implementation protected against EM analysis

Israel Koren, Régis Leveugle, Philippe Maurine, 2013, GLSVLSI '13.

Metric Definition for Circuit Speed Optimization

Philippe Maurine, Daniel Auvergne, Nadine Azémard, 2003, PATMOS.

Exploiting Phase Information in Thermal Scans for Stealthy Trojan Detection

Philippe Maurine, Jean Marc Gallière, Maxime Cozzi, 2018, 2018 21st Euromicro Conference on Digital System Design (DSD).

Speed Indicators for Circuit Optimization

Philippe Maurine, Nadine Azémard, Alexandre Verle, 2005, PATMOS.

Mutual information analysis: higher-order statistical moments, efficiency and efficacy

Philippe Maurine, Mathieu Carbone, Yannick Teglia, 2016, Journal of Cryptographic Engineering.

Collision for Estimating SCA Measurement Quality and Related Applications

Philippe Maurine, Ibrahima Diop, Mathieu Carbone, 2015, CARDIS.

CMOS Gate Sizing under Delay Constraint

Philippe Maurine, Daniel Auvergne, Nadine Azémard, 2003, PATMOS.

Secured Structures for Secured Asynchronous QDI Circuits

Philippe Maurine, Michel Robert, Alin Razafindraibe, 2004 .

Electromagnetic fault injection: the curse of flip-flops

Philippe Maurine, Sébastien Ordas, Ludovic Guillaume-Sage, 2016, Journal of Cryptographic Engineering.

A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation

Robin Wilson, Philippe Maurine, Sylvain Engels, 2007, PATMOS.

Secure D flip-flop against side channel attacks

Philippe Maurine, Sébastien Tiran, Bruno Vaquie, 2012, IET Circuits Devices Syst..

Towards Autonomous Scalable Integrated Systems

Fabien Clermidy, Pascal Benoit, Lionel Torres, 2012 .

Role of Laser-Induced IR Drops in the Occurrence of Faults: Assessment and Simulation

Jean-Max Dutertre, Philippe Maurine, Rodrigo Possamai Bastos, 2017, 2017 Euromicro Conference on Digital System Design (DSD).

Granularity and detection capability of an adaptive embedded Hardware Trojan detection system

Philippe Maurine, Jacques J. A. Fournier, Maxime Lecomte, 2016, 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

Optimization Protocol Based on Low Power Metrics

Philippe Maurine, Nadine Azemard, Alexandre Verle, 2005 .

Full Analyttical Model for delay Performance Estimation in Submicron CMOS

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2001 .

RC on-chip interconnect Performance revisited

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2004 .

SSTA with Cell-to-Cell Delay Correlations

Philippe Maurine, Nadine Azemard, Zeqin Wu, 2010 .

An EM Fault Injection Susceptibility Criterion and Its Application to the Localization of Hotspots

Philippe Maurine, Michel Agoyan, Maxime Madau, 2017, CARDIS.

On-Chip Process Variability Monitoring Flow

Robin Wilson, Philippe Maurine, Sylvain Engels, 2010, J. Low Power Electron..

Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA

Philippe Maurine, Michel Robert, Alin Razafindraibe, 2007, PATMOS.

Secure Triple Track Logic Robustness Against Differential Power and EM Analyses

Lionel Torres, Amine Dehbaoui, Philippe Maurine, 2009 .

A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates

Philippe Maurine, Alin Razafindraibe, P. Maurine, 2007, PATMOS.

Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier

Christian Bernard, Philippe Maurine, Michel Robert, 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

Statistic Implementation of QDI Asynchronous Primitives

Gilles Sicard, Philippe Maurine, Marc Renaudin, 2003, PATMOS.

Temperature Dependency in UDSM Process

Robin Wilson, Philippe Maurine, Nadine Azémard, 2005, PATMOS.

Modeling of Electromagnetic Fault Injection

Philippe Maurine, Mathieu Lisart, Mathieu Dumont, 2019, 2019 12th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo).

Circuit Performance Optimization under Delay Constraints

Philippe Maurine, Nadine Azemard, Alexandre Verle, 2006 .

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 16th International Workshop, PATMOS 2006, Montpellier, France, ... (Lecture Notes in Computer Science)

Johan Vounckx, Philippe Maurine, Nadine Azemard, 2006 .

Attacking Randomized Exponentiations Using Unsupervised Learning

Laurent Imbert, Lionel Torres, Philippe Maurine, 2014, COSADE.

A Method to Design Compact Dual-rail Asynchronous Primitives

Philippe Maurine, Michel Robert, Marc Renaudin, 2005, PATMOS.

Timing Closure Management based on Delay Bound Determination

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2001 .

A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines

Fernando Gehm Moraes, Lionel Torres, Philippe Maurine, 2011, IEEE Design & Test of Computers.

Output transition time modeling of CMOS structures

Philippe Maurine, Daniel Auvergne, Mustapha Rezzoug, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Evaluating the robustness of secure triple track logic through prototyping

Lionel Torres, Philippe Maurine, Michel Robert, 2008, SBCCI '08.

Impacts of Technology Trends on Physical Attacks?

Sylvain Guilley, Philippe Maurine, 2017, COSADE.

Electromagnetic analysis, deciphering and reverse engineering of integrated circuits (E-MATA HARI)

Bruno Robisson, Philippe Maurine, Rachid Omarouayache, 2014, 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC).

Sixteenth International Workshop on Power and Timing Modeling, Optimization and Simulation

Serge Pravossoudovitch, Johan Vounckx, Pascal Nouet, 2006 .

Voltage scaling and body biasing methodology for high performance hardwired LDPC

Robin Wilson, Philippe Maurine, Sylvain Engels, 2010, 2010 IEEE International Conference on Integrated Circuit Design and Technology.

Efficiency of a glitch detector against electromagnetic fault injection

Jean-Max Dutertre, Philippe Maurine, Assia Tria, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Security evaluation of dual rail logic against DPA attacks

Philippe Maurine, Michel Robert, Marc Renaudin, 2006, 2006 IFIP International Conference on Very Large Scale Integration.

Electromagnetic Analysis on RSA Algorithm Based on RNS

Laurent Imbert, Lionel Torres, Philippe Maurine, 2013, 2013 Euromicro Conference on Digital System Design.

Magnitude Squared Coherence based SCA

Philippe Maurine, Sébastien Tiran, 2012, IACR Cryptol. ePrint Arch..

Enhancing Electromagnetic Analysis Using Magnitude Squared Incoherence

Lionel Torres, Amine Dehbaoui, Philippe Maurine, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Statistical timing characterization

Philippe Maurine, Nadine Azémard, Gilles R. Ducharme, 2012, 2012 International Symposium on System on Chip (SoC).

An Electromagnetic imaging technique for Reverse Engineering of Integrated Circuits

Philippe Maurine, Rachid Omarouayache, 2016, 2016 IEEE Asia-Pacific Conference on Applied Electromagnetics (APACE).

Triple Rail Logic Robustness against DPA

Lionel Torres, Philippe Maurine, Michel Robert, 2008, 2008 International Conference on Reconfigurable Computing and FPGAs.

Local and Direct EM Injection of Power Into CMOS Integrated Circuits

Bruno Robisson, Philippe Maurine, Laurent Chusseau, 2011, 2011 Workshop on Fault Diagnosis and Tolerance in Cryptography.

Electromagnetic Fault Injection : How Faults Occur

Philippe Maurine, Mathieu Lisart, Mathieu Dumont, 2019, 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC).

Delay Bound Determination for Timing Closure on CMOS Circuits

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2001 .

Electromagnetic analysis and fault injection onto secure circuits

Régis Leveugle, Jean-Max Dutertre, Bruno Robisson, 2014, 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC).

Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects

Philippe Maurine, Michel Robert, Magali Bastian, 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

Logical effort model extension to propagation delay representation

Robin Wilson, Philippe Maurine, Daniel Auvergne, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Secure Triple Track Logic Robustness Against Differential Power and Electromagnetic Analyses

Lionel Torres, Amine Dehbaoui, Philippe Maurine, 2009 .

Fingerprinting Hardware Security Module Using ICs Radiations

Lionel Torres, Amine Dehbaoui, Philippe Maurine, 2009 .

Delay-correlation-aware SSTA based on conditional moments

Philippe Maurine, Nadine Azémard, Gilles R. Ducharme, 2012, Microelectron. J..

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings

Johan Vounckx, Philippe Maurine, Nadine Azemard, 2006, PATMOS.

A Frequency Leakage Model and its application to CPA and DPA

Philippe Maurine, Yannick Teglia, Michel Agoyan, 2013, IACR Cryptol. ePrint Arch..

Circuit sizing method under delay constraint

Philippe Maurine, Nadine Azémard, Alexandre Verle, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Spectral Coherence Analysis - First Experimental Results -

Amine Dehbaoui, Philippe Maurine, François-Xavier Standaert, 2011, IACR Cryptol. ePrint Arch..

Defining the Maximum Speed of CMOS Gate Library

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2002 .

Countermeasures against EM Analysis

Amine Dehbaoui, Jean-Max Dutertre, Philippe Maurine, 2012 .

Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities

Christian Bernard, Philippe Maurine, Edith Beigné, 2009, PATMOS.

Incoherence analysis and its application to time domain EM analysis of secure circuits

Amine Dehbaoui, Philippe Maurine, Michel Robert, 2010, 2010 Asia-Pacific International Symposium on Electromagnetic Compatibility.

Electromagnetic Activity vs. Logical Activity: Near Field Scans for Reverse Engineering

Philippe Maurine, Marc Lacruche, 2018, CARDIS.

Prototyping Secure Triple Track Logic (STTL) Robustness Against DPA & DEMA on FPGA

Lionel Torres, Philippe Maurine, Michel Robert, 2007 .

Contactless Electromagnetic Active Attack on Ring Oscillator Based True Random Number Generator

Bruno Robisson, Philippe Maurine, Lilian Bossuet, 2012, COSADE.

Differential Power Analysis enhancement with statistical preprocessing

Lionel Torres, Amine Dehbaoui, Philippe Maurine, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Countermeasures against EM analysis for a secured FPGA-based AES implementation

Israel Koren, Régis Leveugle, Philippe Maurine, 2013, 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig).

Simulation and Experimental Demonstration of the Importance of IR-Drops During Laser Fault Injection

Jean-Max Dutertre, Philippe Maurine, Rodrigo Possamai Bastos, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Revisiting Mutual Information Analysis: Multidimensionality, Neural Estimation and Optimality Proofs

Philippe Maurine, Maxime Lecomte, Valence Cristiani, 2023, Journal of Cryptology.

Spatial dependency analysis to extract information from side-channel mixtures: extended version

Philippe Maurine, Hugues Thiebeauld, Aurélien Vasselle, 2021, IACR Cryptol. ePrint Arch..

Exploring flexible and 3D printing technologies for the design of high spatial resolution EM probes

Pascal Nouet, Philippe Maurine, Frédérick Mailly, 2021, 2021 19th IEEE International New Circuits and Systems Conference (NEWCAS).

On the scaling of EMFI probes

Pascal Nouet, Philippe Maurine, Jean Marc Gallière, 2021, 2021 Workshop on Fault Detection and Tolerance in Cryptography (FDTC).

Iterative Method for Performance Prediction Improvement of Integrated Circuits

Philippe Maurine, Jean Marc Gallière, Nadine Azémard, 2021, 2021 XXXVI Conference on Design of Circuits and Integrated Systems (DCIS).

Checking Robustness Against EM Side-Channel Attacks Prior to Manufacturing

Philippe Maurine, Alexandre Sarafianos, Davide Poggi, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Protecting Secure ICs Against Side-Channel Attacks by Identifying and Quantifying Potential EM and Leakage Hotspots at Simulation Stage

Philippe Maurine, Alexandre Sarafianos, Davide Poggi, 2021, COSADE.

SSTA with delay correlations

Philippe Maurine, Gilles Ducharme, Nadine Azemard, 2010, Proceedings of the 8th IEEE International NEWCAS Conference 2010.

Enhancing electromagnetic attacks using spectral coherence based cartography

Lionel Torres, Amine Dehbaoui, Philippe Maurine, 2009 .

Computing delay correlations in SSTA

Philippe Maurine, Nadine Azemard, Zeqin Wu, 2010, 2010 IEEE International Conference on Integrated Circuit Design and Technology.

Switching Current Modeling in CMOS Inverter for Speed and Power Estimation

Philippe Maurine, Daniel Auvergne, Nadine Azemard, 2001 .

Magnitude squared incoherence EM analysis for integrated cryptographic module localisation

Lionel Torres, Amine Dehbaoui, Philippe Maurine, 2009 .