Reum Oh

A snap-back suppressed shorted-anode lateral trench insulated gate bipolar transistor (LTIGBT) with insulated trench collector

Juhyun Oh, D. Chun, Reum Oh, 2011, 2011 IEEE International Symposium on Industrial Electronics.

DSAC: Low-Cost Rowhammer Mitigation Using In-DRAM Stochastic and Approximate Counting Algorithm

Dongho Kim, Reum Oh, C. Yoo, 2023, ArXiv.

3D-Xpath: high-density managed DRAM architecture with cost-effective alternative paths for memory transactions

Min Chul Sung, Sukhan Lee, Kiwon Lee, 2018, PACT.

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution

Reum Oh, Dong-Hak Shin, Jae-Hun Jung, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution

G. Jin, Yong-Cheol Bae, J. Choi, 2017, IEEE Journal of Solid-State Circuits.

Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs

Reum Oh, Yun-Sang Lee, Byunghyun Lee, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM

Reum Oh, Byongwook Na, Jeong-Don Ihm, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

All digital on-chip temperature sensor using dual ring oscillators

Reum Oh, Ji-Woong Jang, Man Young Sung, 2013, 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS).