Zeye Liu

Lightening the Load with Highly Accurate Storage- and Energy-Efficient LightNNs

Diana Marculescu, R. D. Blanton, Ruizhou Ding, 2018, ACM Trans. Reconfigurable Technol. Syst..

Back-End Layout Reflection for Test Chip Design

R. D. Blanton, Zeye Liu, Z. Liu, 2018, 2018 IEEE 36th International Conference on Computer Design (ICCD).

A Low Power Test Pattern Generator for BIST

Zhen Wang, Xiaoying Wang, Feng Liang, 2010, IEICE Trans. Electron..

Differentiable Training for Hardware Efficient LightNNs

Diana Marculescu, R. D. Blanton, Ruizhou Ding, 2018 .

A unified solution to reduce test power and test volume for Test-per-scan schemes

Zhen Wang, Feng Liang, Zeye Liu, 2010, IEICE Electron. Express.

FLightNNs: Lightweight Quantized Deep Neural Networks for Fast and Accurate Inference

Diana Marculescu, R. D. Blanton, Ruizhou Ding, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Improving Test Chip Design Efficiency via Machine Learning

R. D. Blanton, Qicheng Huang, Chenlei Fang, 2019, 2019 IEEE International Test Conference (ITC).

Regularizing Activation Distribution for Training Binarized Deep Networks

Diana Marculescu, Ruizhou Ding, Zeye Liu, 2019, 2019 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR).

A low cost test pattern generator for test-per-clock BIST scheme

Zhen Wang, Feng Liang, Zeye Liu, 2010, IEICE Electron. Express.

CompactNet: High Accuracy Deep Neural Network Optimized for On-Chip Implementation

R. D. Blanton, Zeye Liu, Abhinav Goel, 2018, 2018 IEEE International Conference on Big Data (Big Data).