Rasmita Sahoo

High Performance Ternary Multiplier Using CNTFET

Subhendu Kumar Sahoo, Krishna Dhoot, Rasmita Sahoo, 2018, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Ultra low power full adder circuit using carbon nanotube field effect transistor

Subhendu Kumar Sahoo, Rasmita Sahoo, Koushik Kumar, 2014, 2014 International Conference on Power, Control and Embedded Systems (ICPCES).

High performance ternary adder using CNTFET

Subhendu Kumar Sahoo, Rasmita Sahoo, Manasi Muglikar, 2017, 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS).

Design of an efficient CNTFET using optimum number of CNT in channel region for logic gate implementation

Rasmita Sahoo, S. K. Sahoo, Krishna Chaitanya Sankisa, 2015, 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA).

Design of a High Performance Carry Generation Circuit for Ternary Full Adder Using CNTFET

Subhendu Kumar Sahoo, Rasmita Sahoo, S. K. Sahoo, 2017, 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS).

A CNTFET Based Quaternary Ful1 Adder

Subhendu Kumar Sahoo, Rasmita Sahoo, S. K. Sahoo, 2018, 2018 4th International Conference on Devices, Circuits and Systems (ICDCS).

A High-Speed Radix-64 Parallel Multiplier Using a Novel Hardware Implementation Approach for Partial Product Generation Based on Redundant Binary Arithmetic

Chandra Shekhar, Subhendu Kumar Sahoo, Rasmita Sahoo, 2008, 2008 First International Conference on Emerging Trends in Engineering and Technology.

High-Performance Ternary Adder Using CNTFET

Subhendu Kumar Sahoo, Rasmita Sahoo, Manasi Muglikar, 2016, IEEE Transactions on Nanotechnology.

Simulations of Carbon Nanotube Field Effect Transistors

Rasmita Sahoo, R. R. Mishra, R. Sahoo, 2009 .