H. Bu

35% drive current improvement from recessed-SiGe drain extensions on 37 nm gate length PMOS

D. T. Grider, H. Bu, Y. Kim, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Correlation of device performance to die-level stress variations

Y. Wang, H. Bu, J. Hebb, 2009, 2009 International Workshop on Junction Technology.

Reliability evaluation of HfSiON gate dielectric film with 12.8 /spl Aring/ SiO/sub 2/ equivalent thickness

J. McPherson, R. Khamankar, A. Rotondaro, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Composition control of Hf1−xSixO2 films deposited on Si by chemical-vapor deposition using amide precursors

A. Rotondaro, L. Colombo, T. H. Baum, 2002 .

Effect of nitride sidewall spacer process on boron dose loss in ultrashallow junction formation

S. Banerjee, S. Chakravarthi, C. Machala, 2004 .

Evaluation of the positive biased temperature stress stability in HfSiON gate dielectrics

J. McPherson, S. Aur, P. Nicollian, 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

Interactions of B dopant atoms and Si interstitials with SiO2 films during annealing for ultra-shallow junction formation

S. Banerjee, S. Chakravarthi, S. Dunham, 2005 .

Advanced CMOS transistors with a novel HfSiON gate dielectric

H. Bu, R. Khamankar, T. Grider, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes

B. Hornung, C. Machala, A. Krishnan, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Modeling the effect of source/drain sidewall spacer process on boron ultra shallow junctions

B. Hornung, H. Bu, A. Jain, 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..