John F. Bulzacchelli

发表

A 25 Gb/s burst-mode receiver for low latency photonic switch networks

Mounir Meghelli, Alexander V. Rylyakov, Sergey V. Rylov, 2015, 2015 Optical Fiber Communications Conference and Exhibition (OFC).

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology

Alexander V. Rylyakov, Seongwon Kim, Herschel A. Ainspan, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14nm SOI CMOS

John F. Bulzacchelli, Zeynep Toprak Deniz, Miguel E. Perez, 2019, 2019 IEEE Custom Integrated Circuits Conference (CICC).

Experimental Demonstration of Superconducting

Hae-Seung Lee, John F. Bulzacchelli, James A. Misewich, 2003 .

Superconducting bandpass ?S modulator with 2.23GHz center frequency and 42.6GHz sampling rate

Hae-Seung Lee, John F. Bulzacchelli, James A. Misewich, 2002 .

A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology

Daniel J. Friedman, John F. Bulzacchelli, Timothy O. Dickson, 2009, IEEE J. Solid State Circuits.

A 32-Gb/s backplane transceiver with on-chip AC-coupling and low latency CDR in 32-nm SOI CMOS technology

Mounir Meghelli, Andrea Prati, John F. Bulzacchelli, 2013 .

Root cause identification of an hard-to-find on-chip power supply coupling fail

Franco Stellari, Peilin Song, John F. Bulzacchelli, 2012, 2012 IEEE International Test Conference.

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology

Mounir Meghelli, Andrea Prati, Pier Andrea Francese, 2013, IEEE Journal of Solid-State Circuits.

Equalization for Electrical Links

John F. Bulzacchelli, 2015 .

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology

Thomas Toifl, Christian Menolfi, Andrea Prati, 2012, IEEE Journal of Solid-State Circuits.

Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS"

Mounir Meghelli, Herschel A. Ainspan, John F. Bulzacchelli, 2020, IEEE J. Solid State Circuits.

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE

Chih-Kong Ken Yang, Azita Emami-Neyestanak, Daniel J. Friedman, 2007, IEEE Journal of Solid-State Circuits.

Equalization for Electrical Links: Current Design Techniques and Future Directions

John F. Bulzacchelli, 2015, IEEE Solid-State Circuits Magazine.

A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS

Herschel A. Ainspan, Daniel J. Friedman, Sergey V. Rylov, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 1.8 pJ/bit $16 \times 16\;\text{Gb/s}$ Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration

Mounir Meghelli, Herschel A. Ainspan, Daniel J. Friedman, 2016, IEEE Journal of Solid-State Circuits.

Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS

Zeynep Toprak-Deniz, John F. Bulzacchelli, Michael A. Sperling, 2020, IEEE Journal of Solid-State Circuits.

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects

Yong Liu, Xiaoxiong Gu, Herschel A. Ainspan, 2012, IEEE Journal of Solid-State Circuits.

A 7.5 GS/s flash ADC and a 10.24 GS/s time-interleaved ADC for backplane receivers in 65 nm CMOS

Daniel J. Friedman, Alexander V. Rylyakov, Gu-Yeon Wei, 2015 .

A 28.05Gb/s transceiver using quarter-rate triple-speculation hybrid-DFE receiver with calibrated sampling phases in 32nm CMOS

Thomas Toifl, Mounir Meghelli, Andrea Prati, 2017, 2017 Symposium on VLSI Circuits.

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration

Yong Liu, Mounir Meghelli, Herschel A. Ainspan, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology

Mounir Meghelli, Michael A. Sorna, Sergey V. Rylov, 2012, IEEE J. Solid State Circuits.

A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS

Byungsub Kim, Daniel J. Friedman, Yong Liu, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A superconducting bandpass delta-sigma modulator for direct analog-to-digital conversion of microwave radio

John F. Bulzacchelli, J. Bulzacchelli, 2003 .

Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications

Jean-Olivier Plouchart, Alexander V. Rylyakov, Herschel A. Ainspan, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS

Yong Liu, Daniel J. Friedman, Ankur Agrawal, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology

Thomas Toifl, Christian Menolfi, Andrea Prati, 2012, 2012 IEEE International Solid-State Circuits Conference.

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking

Yong Kim, Kevin G. Stawiasz, Keith A. Jenkins, 2015, IEEE Journal of Solid-State Circuits.

Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage

Seongwon Kim, Mohak Chhabra, Daniel J. Friedman, 2012, IEEE Journal of Solid-State Circuits.

A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology

Mounir Meghelli, Sergey V. Rylov, Jong-Ru Guo, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

Design techniques for CMOS backplane transceivers approaching 30-Gb/s data rates

John F. Bulzacchelli, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor

Kevin G. Stawiasz, Seongwon Kim, Raphael Robertazzi, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS

Byungsub Kim, Daniel J. Friedman, Yong Liu, 2009, IEEE Journal of Solid-State Circuits.

A 32 Gb/s, 4.7 pJ/bit Optical Link With −11.7 dBm Sensitivity in 14-nm FinFET CMOS

Mounir Meghelli, Zeynep Toprak-Deniz, Seongwon Kim, 2018, IEEE Journal of Solid-State Circuits.

A delay-locked loop for clock recovery and data synchronization

John F. Bulzacchelli, 1990 .

22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks

Mounir Meghelli, Alexander V. Rylyakov, Sergey V. Rylov, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS

Yong Liu, Daniel J. Friedman, Ankur Agrawal, 2012, IEEE Journal of Solid-State Circuits.

A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS

Mounir Meghelli, Zeynep Toprak-Deniz, Herschel A. Ainspan, 2020, IEEE Journal of Solid-State Circuits.

A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks

Mounir Meghelli, Alexander V. Rylyakov, Sergey V. Rylov, 2015, IEEE Journal of Solid-State Circuits.

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman, 2015, IEEE Journal of Solid-State Circuits.