Leonardo Ecco

发表

Improved DRAM Timing Bounds for Real-Time DRAM Controllers with Read/Write Bundling

Rolf Ernst, Leonardo Ecco, 2015, 2015 IEEE Real-Time Systems Symposium.

Dynamic admission control for real-time networks-on-chips

Selma Saidi, Rolf Ernst, Adam Kostrzewa, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Tackling the Bus Turnaround Overhead in Real-Time SDRAM Controllers

Rolf Ernst, Leonardo Ecco, 2017, IEEE Transactions on Computers.

Ensuring safety and efficiency in networks-on-chip

Selma Saidi, Rolf Ernst, Adam Kostrzewa, 2017, Integr..

An End-to-End HW/SW Co-Design Methodology to Design Efficient Deep Neural Network Systems using Virtual Models pdf

Andre Guntoro, Michael J. Klaiber, Leonardo Ecco, 2019, INTESA2019.

Enhancing the Utilization of Dot-Product Engines in Deep Learning Accelerators

Leonardo Ecco, Taha Soliman, Armin Runge, 2020, 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW).

Workload-aware shaping of shared resource accesses in mixed-criticality systems

Rolf Ernst, Sebastian Tobuschat, Leonardo Ecco, 2014, 2014 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Architecting high-speed command schedulers for open-row real-time SDRAM controllers

Rolf Ernst, Leonardo Ecco, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Flexible TDM-based resource management in on-chip networks

Selma Saidi, Rolf Ernst, Adam Kostrzewa, 2015, RTNS.

Real-time DRAM throughput guarantees for latency sensitive mixed QoS MPSoCs

Selma Saidi, Rolf Ernst, Adam Kostrzewa, 2015, 10th IEEE International Symposium on Industrial Embedded Systems (SIES).

Adaptive load distribution in mixed-critical Networks-on-Chip

Rolf Ernst, Adam Kostrzewa, Sebastian Tobuschat, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

A mixed critical memory controller using bank privatization and fixed priority scheduling

Selma Saidi, Rolf Ernst, Sebastian Tobuschat, 2014, 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications.

Minimizing DRAM Rank Switching Overhead for Improved Timing Bounds and Performance

Rolf Ernst, Adam Kostrzewa, Leonardo Ecco, 2016, 2016 28th Euromicro Conference on Real-Time Systems (ECRTS).

A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs

Norbert Wehn, Andre Guntoro, Christian Weis, 2021, 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC).