Yu Huang

发表

Fault Dictionary Based Scan Chain Failure Diagnosis

Ruifeng Guo, Wu-Tung Cheng, Yu Huang, 2007, 16th Asian Test Symposium (ATS 2007).

Programmable Logic BIST for At-speed Test

Xijiang Lin, Yu Huang, 2007, 16th Asian Test Symposium (ATS 2007).

Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures

Nilanjan Mukherjee, Yan Dong, Janusz Rajski, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Survey of Scan Chain Diagnosis

Wu-Tung Cheng, Chien-Mo James Li, Ruifeng Guo, 2008, IEEE Design & Test of Computers.

Diagnose Multiple Stuck-at Scan Chain Faults

Wu-Tung Cheng, Ruifeng Guo, Yu Huang, 2008, 2008 13th European Test Symposium.

Using fault model relaxation to diagnose real scan chain defects

Wu-Tung Cheng, Yu Huang, G. Crowell, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Constraint driven pin mapping for concurrent SOC testing

Nilanjan Mukherjee, Sudhakar M. Reddy, Wu-Tung Cheng, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Compactor independent direct diagnosis

Janusz Rajski, Wu-Tung Cheng, Kun-Han Tsai, 2004, 13th Asian Test Symposium.

Session T1B: Tutorial: SoC testing

Janusz Rajski, Yu Huang, 2015, 2015 28th IEEE International System-on-Chip Conference (SOCC).

Effect of IR-Drop on Path Delay Testing Using Statistical Analysis

Yang Wu, Yu Huang, Chunsheng Liu, 2007, 16th Asian Test Symposium (ATS 2007).

On N-detect pattern set optimization

Yu Huang, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

A supervised ANN method for memory failure signature classification

Jianbo Li, Dong Xiang, Wu-Tung Cheng, 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.

Core-clustering based SoC test scheduling optimization

Sudhakar M. Reddy, Wu-Tung Cheng, Yu Huang, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Using fault model relaxation to diagnose real scan chain defects

Wu-Tung Cheng, Yu Huang, Greg Crowell, 2005, ASP-DAC.

Emulating and diagnosing IR-drop by using dynamic SDF

Mark Mohammad Tehranipoor, Wu-Tung Cheng, Ruifeng Guo, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Bad Data Detection and Identification of Hybrid AC/DC Power Systems with Voltage Source Converters Using Deep Belief Network and K-Means Clustering

Fei Zeng, Mingyu Zhai, Hucheng Li, 2019 .

Dynamic Learning Based Scan Chain Diagnosis

Yu Huang, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

SOC test scheduling using simulated annealing

Irith Pomeranz, Sudhakar M. Reddy, Wei Zou, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

Scan Diagnosis and Its Successful Industrial Applications

Wu-Tung Cheng, R. Klingenberg, Yu Huang, 2007, 16th Asian Test Symposium (ATS 2007).

Synthesis of Scan Chains for Netlist Descriptions at RT-Level

Nilanjan Mukherjee, Sudhakar M. Reddy, Wu-Tung Cheng, 2002, J. Electron. Test..

Off-shore outsource DFT vs. build off-shore branch offices

Yu Huang, 2005, IEEE International Conference on Test, 2005..

A Hybrid Flow for Memory Failure Bitmap Classification

Jianbo Li, Dong Xiang, Wu-Tung Cheng, 2012, 2012 IEEE 21st Asian Test Symposium.

Full-circuit SPICE simulation based validation of dynamic delay estimation

Mark Mohammad Tehranipoor, Wu-Tung Cheng, Yu Huang, 2010, 2010 15th IEEE European Test Symposium.

Effect of RTL coding style on testability

Sudhakar M. Reddy, Wu-Tung Cheng, Yu Huang, 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

Diagnosis with Limited Failure Information

Janusz Rajski, Wu-Tung Cheng, Nagesh Tamarapalli, 2006, 2006 IEEE International Test Conference.

Static pin mapping and SOC test scheduling for cores with multiple test sets

Nilanjan Mukherjee, Sudhakar M. Reddy, Wu-Tung Cheng, 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

Diagnosis and Layout Aware (DLA) Scan Chain Stitching

Yu Hu, Xiaowei Li, Jing Ye, 2015, IEEE Trans. Very Large Scale Integr. Syst..

Study of optimal commercial building envelope design in cooling-dominant climates

Yu Huang, 2014 .

Modeling of post-tensioned one-way and two-way slabs with unbonded tendons

Yu Huang, Thomas H.-K. Kang, Uksun Kim, 2014 .

Improving the proportion of at-speed tests in scan BIST

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

A complete test set to diagnose scan chain failures

Wu-Tung Cheng, Ruifeng Guo, Yu Huang, 2007, 2007 IEEE International Test Conference.

Detection and Diagnosis of Static Scan Cell Internal Defect

Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, 2008, 2008 IEEE International Test Conference.

Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns

Wu-Tung Cheng, Ruifeng Guo, Yu Huang, 2009, 2009 Asian Test Symposium.

Diagnosis of Defects on Scan Enable and Clock Trees

Yu Huang, Keith Gallie, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Enhance Profiling-Based Scan Chain Diagnosis by Pattern Masking

Wu-Tung Cheng, Yu Huang, Yu Huang, 2010, 2010 19th IEEE Asian Test Symposium.

Bit selection algorithm suitable for high-volume production of SRAM-PUF

Mark Mohammad Tehranipoor, Domenic Forte, Kan Xiao, 2014, 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

Diagnose compound scan chain and system logic defects

Wu-Tung Cheng, Ruifeng Guo, Yu Huang, 2007, 2007 IEEE International Test Conference.

Test cycle power optimization for scan-based designs

Wu-Tung Cheng, Kun-Han Tsai, Yu Huang, 2010, 2010 IEEE International Test Conference.

Compressed pattern diagnosis for scan chain failures

Janusz Rajski, Wu-Tung Cheng, Yu Huang, 2005, IEEE International Conference on Test, 2005..

A RTL Testability Analyzer Based on Logical Virtual Prototyping

Yu Huang, G. Aldrich, N. Mukherjee, 2007, 16th Asian Test Symposium (ATS 2007).

Resource allocation and test scheduling for concurrent test of core-based SOC design

Nilanjan Mukherjee, Sudhakar M. Reddy, Wu-Tung Cheng, 2001, Proceedings 10th Asian Test Symposium.

Debugging clock-data race failures caused by vulnerable design

Ruifeng Guo, Wu-Tung Cheng, Yu Huang, 2008, 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

On Improving Diagnostic Test Generation for Scan Chain Failures

Sudhakar M. Reddy, Wu-Tung Cheng, Xun Tang, 2009, 2009 Asian Test Symposium.

Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis

Yu Hu, Fei Wang, Xiaowei Li, 2008, 2008 17th Asian Test Symposium.

Reducing Scan Shift Power at RTL

Wu-Tung Cheng, Jennifer Dworak, Xijiang Lin, 2008, 26th IEEE VLSI Test Symposium (vts 2008).

Intermittent scan chain fault diagnosis based on signal probability analysis

Wu-Tung Cheng, Yu Huang, Cheng-Ju Hsieh, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Efficient diagnosis for multiple intermittent scan chain hold-time faults

Wu-Tung Cheng, Yu Huang, Cheng-Ju Hsieh, 2003, 2003 Test Symposium.

Using embedded infrastructure IP for SOC post-silicon verification

Wu-Tung Cheng, Yu Huang, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Statistical diagnosis for intermittent scan chain hold-time fault

Sudhakar M. Reddy, Wu-Tung Cheng, Yu Huang, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

EDT bandwidth management - Practical scenarios for large SoC designs

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2013, 2013 IEEE International Test Conference (ITC).

Diagnosis and Layout Aware (DLA) scan chain stitching

Yu Hu, Xiaowei Li, Jing Ye, 2013, 2013 IEEE International Test Conference (ITC).

On RTL scan design

Nilanjan Mukherjee, Sudhakar M. Reddy, Wu-Tung Cheng, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells

Xijiang Lin, Yu Huang, 2008, J. Electron. Test..