H. Bender

发表

FIRST COMMISSIONING EXPERIMENTS AT DARHT-II

Bechtel Nevada, Carl Ekdahl, E. O. Abeyta, 2004 .

High-mobility Si1−xGex-channel PFETs: Layout dependence and enhanced scalability, demonstrating 90% performance boost at narrow widths

C. Ortolland, L. Witters, H. Bender, 2010, 2010 Symposium on VLSI Technology.

Gate-all-around NWFETs vs. triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS

E. Simoen, G. Hellings, E. Vecchio, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

0.5 nm EOT low leakage ALD SrTiO3 on TiN MIM capacitors for DRAM applications

S. Van Elshocht, B. Kaczer, H. Bender, 2008, 2008 IEEE International Electron Devices Meeting.

A simple and effective light trapping technique for polycrystalline silicon solar cells

H. Bender, H. Bender, G. Willeke, 1992 .

Strained Germanium quantum well pMOS FinFETs fabricated on in situ phosphorus-doped SiGe strain relaxed buffer layers using a replacement Fin process

L. Witters, N. Waldron, N. Collaert, 2013, 2013 IEEE International Electron Devices Meeting.

Beyond interface: The impact of oxide border traps on InGaAs and Ge n-MOSFETs

R. Degraeve, D. Lin, N. Collaert, 2012, 2012 International Electron Devices Meeting.

Polycrystalline silicon solar cells with a mechanically formed texturization

Johan Nijs, Robert Mertens, H. Bender, 1993 .

Enabling 3X nm DRAM: Record low leakage 0.4 nm EOT MIM capacitors with novel stack engineering

B. Kaczer, B. Govoreanu, H. Bender, 2010, 2010 International Electron Devices Meeting.

Performance and reliability of high-mobility Si0.55Ge0.45 p-channel FinFETs based on epitaxial cladding of Si Fins

L. Witters, N. Collaert, H. Bender, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Analysis of dopant diffusion and defects in SiGe channel Quantum Well for Laser annealed device using an atomistic kinetic Monte Carlo approach

G. Hellings, L. Witters, H. Bender, 2011, 2011 International Electron Devices Meeting.

Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

B. Parvais, B. Kaczer, E. Simoen, 2016, 2016 IEEE Symposium on VLSI Technology.

Low temperature deposition of 2D WS2 layers from WF6 and H2S precursors: impact of reducing agents.

S. De Gendt, S. Van Elshocht, H. Bender, 2015, Chemical communications.

Full-field EUV and immersion lithography integration in 0.186μm2 FinFET 6T-SRAM cell

B. Parvais, R. Rooyackers, K. Ronse, 2008, 2008 IEEE International Electron Devices Meeting.

Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration

D. Mocuta, H. Bender, R. Ritzenthaler, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Metal Gate Technology using a Dy2O3 Dielectric Cap Approach for multiple-VT in NMOS FinFETs

S. Van Elshocht, B. Kaczer, P. Lehnen, 2007, 2007 IEEE International SOI Conference.

Advanced a-VMCO resistive switching memory through inner interface engineering with wide (>102) on/off window, tunable μA-range switching current and excellent variability

B. Govoreanu, H. Bender, M. Jurczak, 2016, 2016 IEEE Symposium on VLSI Technology.

A novel sample preparation technique for cross-sectional tem investigation of integrated circuits

C. Claeys, H. Bender, R. Van Overstraeten, 1983 .

8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS

L. Witters, H. Bender, T. Chiarella, 2010, 2010 Symposium on VLSI Technology.

Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

L. Witters, D. Mocuta, N. Collaert, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

A. Brand, P. Eyben, L. Witters, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Determination of stress in shallow trench isolation for deep submicron MOS devices by UV Raman spectroscopy

R. Rooyackers, I. De Wolf, H. Bender, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Defects in AS-Grown Silicon and their Evolution During Heat Treatments

H. Bender, Jan Vanhellemont, G. Kissinger, 1997 .

Conductive-AFM tomography for 3D filament observation in resistive switching devices

L. Goux, H. Bender, W. Vandervorst, 2013, 2013 IEEE International Electron Devices Meeting.

Dual Work Function Phase Controlled Ni-FUSI CMOS (NiSi NMOS, Ni2Si or Ni31Si12 PMOS): Manufacturability, Reliability & Process Window Improvement by Sacrificial SiGe Cap

S. Locorotondo, H. Bender, T. Chiarella, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Scaling of high-k dielectrics towards sub-1nm EOT

S. De Gendt, D. Pique, S. Van Elshocht, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

Ge nFET with high electron mobility and superior PBTI reliability enabled by monolayer-Si surface passivation and La-induced interface dipole formation

L. Witters, N. Collaert, S. Sioncke, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

High-k dielectrics for future generation memory devices (Invited Paper)

Christoph Adelmann, Ben Kaczer, Dirk Wouters, 2009 .

Strain Enhanced nMOS Using In Situ Doped Embedded $\hbox{Si}_{1 - x}\hbox{C}_{x}$ S/D Stressors With up to 1.5% Substitutional Carbon Content Grown Using a Novel Deposition Process

H. Bender, S. Biesemans, D. Shamiryan, 2008, IEEE Electron Device Letters.

Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal

M. Badaroglu, L. Witters, D. Mocuta, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Highly scalable effective work function engineering approach for multi-VT modulation of planar and FinFET-based RMG high-k last devices for (Sub-)22nm nodes

E. Simoen, E. Vecchio, H. Bender, 2013, 2013 Symposium on VLSI Technology.

Demonstration of scaled 0.099µm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

R. Rajagopalan, K. Ronse, S. Locorotondo, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Gate-last vs. gate-first technology for aggressively scaled EOT logic/RF CMOS

H. Bender, G. Eneman, N. Horiguchi, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates

C. Merckling, D. Lin, N. Waldron, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.