Satyajit Desai

Process variation aware DRAM design using block based adaptive body biasing algorithm

Sanghamitra Roy, Koushik Chakraborty, Satyajit Desai, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

Using Adaptive Body Biasing for Robust Process Variation Aware DRAM Design

Sanghamitra Roy, Satyajit Desai, Sanghamitra Roy, 2013, Journal of Low Power Electronics.

Process variation aware DRAM (Dynamic Random Access Memory) design using block-based adaptive body biasing algorithm

Satyajit Desai, S. Desai, 2012 .