Giuseppe Natale

A polyhedral model-based framework for dataflow implementation on FPGA devices of Iterative Stencil Loops

Marco D. Santambrogio, Donatella Sciuto, Giulio Stramondo, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

On How to Accelerate Iterative Stencil Loops

Marco D. Santambrogio, Donatella Sciuto, Giuseppe Natale, 2015, ACM Trans. Archit. Code Optim..

A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project

Michael Hübner, Marco D. Santambrogio, Dirk Stroobandt, 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

A Feedback-Based Design Space Exploration Subsystem for the Automation of Architectures Synthesis on Proprietary FPGA Toolchains

Marco D. Santambrogio, Giuseppe Natale, Alessandro Pappalardo, 2017, 2017 Euromicro Conference on Digital System Design (DSD).

A Framework with Cloud Integration for CNN Acceleration on FPGA Devices

Marco D. Santambrogio, Marco Bacis, Giuseppe Natale, 2018, 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW).

Optimizing streaming stencil time-step designs via FPGA floorplanning

Marco D. Santambrogio, Antonio Miele, Marco Rabozzi, 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project

Marco D. Santambrogio, Emanuele Del Sozzo, Alberto Scolari, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

An FPGA-Based Acceleration Methodology and Performance Model for Iterative Stencils

Marco D. Santambrogio, Enrico Reggiani, Giuseppe Natale, 2018, 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW).

On How to Design Dataflow FPGA-Based Accelerators for Convolutional Neural Networks

Marco D. Santambrogio, Marco Bacis, Giuseppe Natale, 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).