Dongsuk Jeon

发表

David Blaauw, Dennis Sylvester, Mingoo Seok, 2011 .

Live demonstration: A 128-channel spike sorting processor featuring 0.175 μW and 0.0033 mm2 per Channel in 65-nm CMOS

Dennis Sylvester, Anh-Tuan Do, Tony Tae-Hyoung Kim, 2016, 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

A Fast Finite Field Multiplier for SIKE pdf

Dongsuk Jeon, Yeonsoo Jeon, 2020, ArXiv.

8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment

David Blaauw, Dennis Sylvester, Seokhyeon Jeong, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A 470mV 2.7mW feature extraction-accelerator for micro-autonomous vehicle navigation in 28nm CMOS

David Blaauw, Dennis Sylvester, Yejoong Kim, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring

David Blaauw, Dennis Sylvester, Yejoong Kim, 2015, IEEE Journal of Solid-State Circuits.

A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector

David Blaauw, Dennis Sylvester, Seokhyeon Jeong, 2018, IEEE Journal of Solid-State Circuits.

Design techniques for ultra-efficient computing

Dongsuk Jeon, 2016, 2016 International SoC Design Conference (ISOCC).

Power-up control techniques for reliable SRAM PUF

Dongsuk Jeon, Dong-Woo Jee, J. Y. Lee, 2019, IEICE Electron. Express.

7.6 A 65nm 236.5nJ/Classification Neuromorphic Processor with 7.5% Energy Overhead On-Chip Learning Using Direct Spike-Only Feedback

Dongsuk Jeon, Juyun Lee, Jeongwoo Park, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A 23-mW Face Recognition Processor with Mostly-Read 5T Memory in 40-nm CMOS

David Blaauw, Xiaolong Wang, Hao Yu, 2017, IEEE Journal of Solid-State Circuits.

Design Methodology for Voltage-Overscaled Ultra-Low-Power Systems

David Blaauw, Dennis Sylvester, Mingoo Seok, 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 120nW 8b sub-ranging SAR ADC with signal-dependent charge recycling for biomedical applications

David Blaauw, Dennis Sylvester, Grant H. Kruger, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

Energy-optimized high performance FFT processor

David Blaauw, Chaitali Chakrabarti, Dennis Sylvester, 2011, 2011 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

Energy-Efficient Digital Signal Processing Hardware Design.

Dongsuk Jeon, 2014 .

A 0.6V, 8mW 3D Vision Processor for a Navigation Device for the Visually Impaired

Nathan Ickes, Anantha Chandrakasan, Daniela Rus, 2016 .

A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory

David Blaauw, Xiaolong Wang, Hao Yu, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

A 65-nm Neuromorphic Image Classification Processor With Energy-Efficient Training Through Direct Spike-Only Feedback

Dongsuk Jeon, J. Y. Lee, Jeongwoo Park, 2020, IEEE Journal of Solid-State Circuits.

An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS

David Blaauw, Dennis Sylvester, Yejoong Kim, 2014, IEEE Journal of Solid-State Circuits.

Circuit techniques for miniaturized biomedical sensors

David Blaauw, Dennis Sylvester, Jae-Yoon Sim, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

A low-power VGA full-frame feature extraction processor

David Blaauw, Dennis Sylvester, Yejoong Kim, 2013, 2013 IEEE International Conference on Acoustics, Speech and Signal Processing.

Microarchitecture-Aware Code Generation for Deep Learning on Single-ISA Heterogeneous Multi-Core Mobile Processors

Yongjun Park, Dongsuk Jeon, Yongin Kwon, 2019, IEEE Access.

A Modified Serial Commutator Architecture for Real-Valued Fast Fourier Transform

Dongsuk Jeon, Sungjin Park, 2020, 2020 IEEE Workshop on Signal Processing Systems (SiPS).

Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design

David Blaauw, Chaitali Chakrabarti, Dennis Sylvester, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

Extending energy-saving voltage scaling in ultra low voltage integrated circuit designs

David Blaauw, Chaitali Chakrabarti, Dennis Sylvester, 2012, 2012 IEEE International Conference on IC Design & Technology.

Enhancing Reliability of Analog Neural Network Processors

Dongsuk Jeon, Kwanghyun Shin, Suhong Moon, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 128-channel spike sorting processor featuring 0.175 µW and 0.0033 mm2 per channel in 65-nm CMOS

Dennis Sylvester, Anh-Tuan Do, Tony Tae-Hyoung Kim, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

Improving GPU Multitasking Efficiency Using Dynamic Resource Sharing

Yongjun Park, Jason Jong Kyu Park, Dongsuk Jeon, 2019, IEEE Computer Architecture Letters.

A Super-Pipelined Energy Efficient Subthreshold 240 MS/s FFT Core in 65 nm CMOS

David Blaauw, Chaitali Chakrabarti, Dennis Sylvester, 2012, IEEE Journal of Solid-State Circuits.

A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining

David Blaauw, Chaitali Chakrabarti, Dennis Sylvester, 2011, 2011 IEEE International Solid-State Circuits Conference.

An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With $0.175~\mu$ W/Channel in 65-nm CMOS

Dennis Sylvester, Tony Tae-Hyoung Kim, Dongsuk Jeon, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Real-Time Denoising and Dereverberation wtih Tiny Recurrent U-Net

Hyeong-Seok Choi, Dongsuk Jeon, Hoon Heo, 2021, ICASSP 2021 - 2021 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

A 40nm 4.81TFLOPS/W 8b Floating-Point Training Processor for Non-Sparse Neural Networks Using Shared Exponent Bias and 24-Way Fused Multiply-Add Tree

Sunwoo Lee, Dongsuk Jeon, Jeongwoo Park, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

Fast Automatic Circuit Optimization Using Deep Learning

Dongsuk Jeon, Jaeha Kim, Jiwoo Hong, 2021, 2021 18th International SoC Design Conference (ISOCC).

A Neural Network Training Processor With 8-Bit Shared Exponent Bias Floating Point and Multiple-Way Fused Multiply-Add Trees

Sunwoo Lee, Dongsuk Jeon, Jeongwoo Park, 2022, IEEE Journal of Solid-State Circuits.

Dynamic Block-Wise Local Learning Algorithm for Efficient Neural Network Training

Sunwoo Lee, Dongsuk Jeon, Gwangho Lee, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.