Hyung-Joon Chi

发表

A 3Gb/s 8b single-ended transceiver for 4-drop DRAM interface with digital calibration of equalization skew and offset coefficients

Hong-June Park, Seung-Jun Bae, Hyung-Joon Chi, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

Sukhyun Lim, Jin-Hun Jang, Dukha Park, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A CMOS Single-Ended Transceiver for 4-Drop DRAM Interface

Hong-June Park, Seung-Jun Bae, Hyung-Joon Chi, 2006 .

6.3: A Low-EMI 2Gbps ClockAlignedtoData IntraPanel Interface (CADI) for TFT-LCD with the VSYNC-Embedded Clock and Equalization

Hong-June Park, Hee-Sub Lee, Young-Ho Choi, 2010 .

A 2Gb/s 2-tap DFE receiver for mult-drop single-ended signaling systems with reduced noise

Hong-June Park, Seung-Jun Bae, Hyung-Joon Chi, 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL

Jae-Yoon Sim, Hong-June Park, Hee-Sub Lee, 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 0.12GHz-1.4GHz DLL-based clock generator with a multiplied 4-phase clock using a 0.18um CMOS process

Hong-June Park, Jae-Yoon Sim, Jae-Seung Lee, 2006 .

A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface

Jae-Yoon Sim, Hong-June Park, Seung-Jun Bae, 2011, IEEE Journal of Solid-State Circuits.

A 4-Gb/s Single-Ended Transmitter for DRAM Interface with Pre-Emphasis and Low Skew Multiplexing using a 0.25um CMOS Process

Hong-June Park, Seung-Jun Bae, Hyung-Joon Chi, 2004 .

A CMOS Multi-phase Delay-Locked Loop for storage media using a 0.18-㎛ CMOS Process

Hong-June Park, Hee-Sub Lee, Hyung-Joon Chi, 2005 .

A 32/16 Multi-Phase Delay-Locked Loop for DVD Application

Hong-June Park, Hee-Sub Lee, Seung-Jun Bae, 2005 .

A 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling

Jae-Yoon Sim, Hong-June Park, Seung-Jun Bae, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration

Jae-Yoon Sim, Hong-June Park, Seung-Jun Bae, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Serpentine Microstrip Lines With Zero Far-End Crosstalk for Parallel High-Speed DRAM Interfaces

Jae-Yoon Sim, Hong-June Park, Hyung-Joon Chi, 2010, IEEE Transactions on Advanced Packaging.