Zhigang Mao

发表

Novel Mixed Codes for Multiple-Cell Upsets Mitigation in Static RAMs

Qiang Zhao, Jing Guo, Liyi Xiao, 2013, IEEE Micro.

Companding schemes based on transforming signal statistics into trigonal distributions for PAPR reduction in OFDM systems

Bin Zhou, Zhigang Mao, Zhiqiang Gao, 2011, Int. J. Commun. Syst..

Soft-Input Soft-Output Parallel Stack Algorithm for MIMO Detection

Zhigang Mao, Guanghui He, Jun Ma, 2014 .

Improved Iterative Receiver for Co-channel Interference Suppression in MIMO-OFDM Systems

Guanghui He, Zhigang Mao, Zhiting Yan, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Parallel SER analysis for combinational and sequential standard cell circuits

Zhigang Mao, Weiguang Sheng, Jian-Fei Jiang, 2016, Microelectron. J..

Area-efficient HEVC IDCT/IDST architecture for 8K × 4K video decoding

Guanghui He, Zhigang Mao, Liang Hong, 2016, IEICE Electron. Express.

Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms

Shi-Jie Wen, Lei He, Zhigang Mao, 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

Automated design method for parameters optimization of CMOS analog circuits based on adaptive genetic algorithm

Zhigang Mao, Jianhai Yu, 2007, 2007 7th International Conference on ASIC.

A Thermal-Aware Task Mapping Algorithm for Coarse Grain Reconfigurable Computing System

Zhigang Mao, Weiguang Sheng, Weifeng He, 2012 .

Robust design of sub-threshold flip-flop cells for wireless sensor network

Wei Jin, Zhigang Mao, Weifeng He, 2011, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip.

Analysis of electromechanical interface model for liquid floated micro-gyroscope

Xiaowei Liu, Zhigang Mao, Wen Zuo, 2013, The 8th Annual IEEE International Conference on Nano/Micro Engineered and Molecular Systems.

A new algorithm for retiming-based partial scan

Zhigang Mao, Yizheng Ye, Zulan Huang, 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

Improved Max-Log-MAP BICM-IDD receiver for MIMO systems

Xi Chen, Guanghui He, Zhigang Mao, 2014, IEICE Electron. Express.

A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard

Zhigang Mao, Liang Hong, Hui Zhu, 2013, IEICE Electron. Express.

Fault detection and redundancy design for TSVs in 3D ICs

Zhigang Mao, Qin Wang, Jing Xie, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling

Liyi Xiao, Zhigang Mao, Weiguang Sheng, 2008, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008).

Low Complexity Algorithm and VLSI Design of Joint Demosaicing and Denoising for Digital Still Camera

Hong Liang, Zhigang Mao, Wei Jin, 2014 .

Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code

Qiang Zhao, Jing Guo, Liyi Xiao, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations

Yongxin Zhu, Guanghui He, Zhigang Mao, 2019, ACM Trans. Design Autom. Electr. Syst..

TSVs-aware floorplanning for 3D integrated circuit

Zhigang Mao, Qin Wang, Jing Xie, 2013, 2013 IEEE 10th International Conference on ASIC.

Statistical estimation and evaluation for communication mapping in Network-on-Chip

Yongxin Zhu, Zhigang Mao, Weifeng He, 2010, Integr..

A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR core based on wide-pulsed-latch pipelines

Zhigang Mao, Mingoo Seok, Weifeng He, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing

Guanghui He, Zhigang Mao, Zhiting Yan, 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Block Cipher Circuit Design against Power Analysis

Zhimin Zhang, Zhigang Mao, Zheng Guo, 2013, 2013 Ninth International Conference on Computational Intelligence and Security.

An efficient 90nm technology-node GHz transceiver of on-chip global interconnect

Zhigang Mao, Jian-Fei Jiang, Zaixiao Zheng, 2011, 2011 9th IEEE International Conference on ASIC.

High performance parallel turbo decoder with configurable interleaving network for LTE application

Guanghui He, Zhigang Mao, Zhiting Yan, 2016, Integr..

Reliability analysis of memories suffering MBUs for the effect of negative bias temperature instability

Shanshan Liu, Liyi Xiao, Zhigang Mao, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

An energy-efficient and scalable eDRAM-based register file architecture for GPGPU

Minyi Guo, Yao Lu, Zhigang Mao, 2013, ISCA.

Design and VLSI Architecture of a Channel Equalizer Based on Adaptive Modulation for IEEE 802.11a WLAN

Wei Zhong, Zhigang Mao, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology

Hai Huang, Shanshan Liu, Liyi Xiao, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Extend orthogonal Latin square codes for 32-bit data protection in memory applications

Shanshan Liu, Liyi Xiao, Zhigang Mao, 2016, Microelectron. Reliab..

Novel Low-Power and Highly Reliable Radiation Hardened Memory Cell for 65 nm CMOS Technology

Jing Guo, Liyi Xiao, Zhigang Mao, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

Parasitic Parameters Impacts Investigation on Soft Error Rate by a Circuit Level Framework

Zhigang Mao, Weiguang Sheng, Zhongyuan Zhao, 2015, 2015 IEEE 21st Pacific Rim International Symposium on Dependable Computing (PRDC).

Redundancy based interconnect duplication to mitigate soft errors in SRAM-based FPGAs

Xin Chen, Zhigang Mao, Weifeng He, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Contention and energy aware mapping for real-time applications on Network-on-Chip

Zhigang Mao, Weifeng He, Naifeng Jing, 2012, 2012 International SoC Design Conference (ISOCC).

On-chip structure and addressing scheme design for 2-D block data processing in a 64-core array system

Zhigang Mao, Jing Xie, Huimin Xing, 2011, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip.

Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory

Wei Jin, Zhigang Mao, Zhongyuan Zhao, 2016, 2016 International Conference on Field-Programmable Technology (FPT).

Mitigating FPGA interconnect soft errors by in-place LUT inversion

Zhigang Mao, Lei He, Weifeng He, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Parallel SFSD MIMO detection with SOFT-HARD combination enumeration

Jun Ma, Zhigang Mao, Jianpeng Yu, 2011, 2011 IEEE Workshop on Signal Processing Systems (SiPS).

A pre-emphasis circuit design for high speed on-chip global interconnect

Zhigang Mao, Weiguang Sheng, Weifeng He, 2012, 2012 IEEE International Symposium on Circuits and Systems.

An adaptive motion estimation algorithm based on evolution strategies with correlated mutations

Hui Wang, Zhigang Mao, 2004, ICIP.

A novel soft error sensitivity characterization technique based on simulated fault injection and constrained association analysis

Liyi Xiao, Zhigang Mao, Weiguang Sheng, 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

Full Automatic Task Compilation Flow from C to REmus Coarse Grain Reconfigurable Media Processor

Zhigang Mao, Jianfei Jiang, Weiguang Sheng, 2011 .

Versatile and Efficient Techniques for Speeding-Up Circuit Level Simulated Fault-Injection Campaigns

Liyi Xiao, Zhigang Mao, Weiguang Sheng, 2008, 2008 14th IEEE Pacific Rim International Symposium on Dependable Computing.

mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator

Zhigang Mao, Weiguang Sheng, Zhongyuan Zhao, 2019, 2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

A novel architecture scheme with adaptive pipeline coupling technique for DSP processor design

Zhigang Mao, Zheng Tang, Jing Xie, 2013, 2013 IEEE 10th International Conference on ASIC.

A novel hardware prefetching scheme exploiting 2-D spatial locality in multimedia applications

Zhigang Mao, Jin Huang, Jing Xie, 2011, 2011 9th IEEE International Conference on ASIC.

Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications

Hai Huang, Liyi Xiao, Zhigang Mao, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects

Zhigang Mao, Weiguang Sheng, Qin Wang, 2016, J. Circuits Syst. Comput..

A method in CMOS analog circuit optimization by genetic algorithm

Zhigang Mao, Jianhai Yu, 2009 .

Cyclicity Restoration Using Tentative Signals for OFDM-Based WLAN Systems

Zhigang Mao, Wei Zhong, 2006, 2006 International Conference on Communications, Circuits and Systems.

A reconfigurable linear array processor architecture for data parallel and computation intensive applications

Yucheng Liu, Zhigang Mao, Jing Xie, 2011, 2011 9th IEEE International Conference on ASIC.

A 230mV 8-bit sub-threshold microprocessor for wireless sensor network

Wei Jin, Zhigang Mao, Weifeng He, 2011, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip.

MBSS:A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs

Zhigang Mao, Weiguang Sheng, Zhongyuan Zhao, 2018, 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

A Scalable Frame-Level Pipelined Architecture for FSBM Motion Estimation

Chi-Ying Tsui, Zhigang Mao, Weifeng He, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

A thermal-aware task mapping flow for coarse-grain dynamic reconfigurable processor

Zhigang Mao, Li Xie, Weifeng He, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

Fault Secure Encoder and Decoder Designs for Matrix Codes

Shanshan Liu, Jing Guo, Liyi Xiao, 2015, 2015 14th International Conference on Computer-Aided Design and Computer Graphics (CAD/Graphics).

Novel O-GEHL Based Hyperblock Predictor for EDGE Architectures

Zhigang Mao, Mingyan Yu, Bing Yang, 2012, NAS.

Effective multi-standard macroblock prediction VLSI design for reconfigurable multimedia systems

Guanghui He, Jun Ma, Zhigang Mao, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

A static-placement, dynamic-issue framework for CGRA loop accelerator

Zhigang Mao, Weiguang Sheng, Zhongyuan Zhao, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

A crosstalk avoidance scheme based on re-layout of signal TSV

Zhigang Mao, Qin Wang, Jing Xie, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms

Lei He, Zhigang Mao, Weifeng He, 2013, TODE.

Statistical Estimation for Total Communication Load in Application-Specific Network-on-Chip

Yongxin Zhu, Zhigang Mao, Naifeng Jing, 2009, 2009 International Conference on Embedded Software and Systems.

Area and throughput efficient IDCT/IDST architecture for HEVC standard

Guanghui He, Zhigang Mao, Liang Hong, 2014, ISCAS.

A soft-output parallel stack algorithm for MIMO detection

Guanghui He, Jun Ma, Zhigang Mao, 2013, SiPS 2013 Proceedings.

Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic

Zhigang Mao, Volkan Kursun, Weifeng He, 2017, Microelectron. J..

A point to point inter-cluster communication network in clustered superscalar processor

Zhigang Mao, Xiao Chen, Bing Yang, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

Generalized interleaving network based on configurable QPP architecture for parallel turbo decoder

Guanghui He, Jun Ma, Zhigang Mao, 2011, 2011 IEEE Workshop on Signal Processing Systems (SiPS).

Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm

Zhigang Mao, Weiguang Sheng, Weifeng He, 2012, 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum.

Dynamic data split: A crosstalk suppression scheme in TSV-based 3D IC

Zhigang Mao, Qin Wang, Jian-Fei Jiang, 2017, Integr..

An application specific NoC mapping for optimized delay

Zhigang Mao, Wenbiao Zhou, Yan Zhang, 2006, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006..

Pareto based Multi-objective Mapping IP Cores onto NoC Architectures

Yan Zhang, Zhigang Mao, Wenbiao Zhou, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

Quantization issues in turbo decoding

Zhigang Mao, Yanmin Chen, Xizhong Lou, 2005, Proceedings. 2005 International Conference on Communications, Circuits and Systems, 2005..

A design method in CMOS operational amplifier optimization based on adaptive genetic algorithm

Zhigang Mao, Jianhai Yu, 2009 .

Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors

Zhigang Mao, Volkan Kursun, Hailong Jiao, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

A general statistical estimation for application mapping in Network-on-Chip

Zhigang Mao, Weifeng He, Naifeng Jing, 2011, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip.

Low redundancy matrix-based codes for adjacent error correction with parity sharing

Jie Li, Shanshan Liu, Liyi Xiao, 2017, 2017 18th International Symposium on Quality Electronic Design (ISQED).

Delay hidden techniques based on configuration contexts reuse and differential reconfiguration in coarse-grained reconfigurable processor

Zhigang Mao, Weiguang Sheng, Haopeng Liu, 2013, 2013 IEEE 10th International Conference on ASIC.

Test pattern generation for column compression multiplier

Zhigang Mao, Yizheng Ye, Yuliang Deng, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Optimizing the data placement and transformation for multi-bank CGRA computing system

Zhigang Mao, Weiguang Sheng, Qin Wang, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Fault modeling and characteristics of SRAM-based FPGAs (abstract only)

Chun Zhang, Zhigang Mao, Lei He, 2011, FPGA '11.

Soft Error Hardened Memory Design for Nanoscale Complementary Metal Oxide Semiconductor Technology

Xu Wang, Tianqi Wang, Shanshan Liu, 2015, IEEE Transactions on Reliability.

An efficient VLSI architecture for extended variable block sizes motion estimation

Zhigang Mao, Weiwei Chen, Weifeng He, 2010, 23rd IEEE International SOC Conference.

Low Complexity Time Domain Interleaved Partitioning Partial Transmit Sequence Scheme for Peak-to-Average Power Ratio Reduction of Orthogonal Frequency Division Multiplexing Systems

Bin Zhou, Zhigang Mao, Jinxiang Wang, 2011, Wirel. Pers. Commun..

A Hybrid Anti-Collision Algorithm for RFID with Enhanced Throughput and Reduced Memory Consumption

Yongxin Zhu, Zhigang Mao, Jing Xie, 2008, 2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing.

Resource-saving compile flow for coarse-grained reconfigurable architectures

Zhigang Mao, Weiguang Sheng, Zhongyuan Zhao, 2015, 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

On the Leakage between Arithmetic Components of DES Algorithm

Zhigang Mao, Zheng Guo, Junrong Liu, 2015 .

A Restoration Algorithm for Images Contaminated by Impulse Noise

Peng Liu, Yan Zhang, Zhigang Mao, 2006, Journal of Computer Research and Development.

An Improved Frame-Level Pipelined Architecture for High Resolution Video Motion Estimation

Zhigang Mao, Weifeng He, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Resource constrained mapping of data flow graphs onto coarse-grained reconfigurable array

Zhigang Mao, Weifeng He, Naifeng Jing, 2010, 23rd IEEE International SOC Conference.

Design optimization for capacitive-resistively driven on-chip global interconnect

Jizeng Wei, Zhigang Mao, Qin Wang, 2015, IEICE Electron. Express.

Tentative Decision Based Low Complexity Equalization for OFDM Systems with Insufficient Cyclic Prefix

Zhigang Mao, Wei Zhong, 2005, 2005 5th International Conference on Information Communications & Signal Processing.

Impact of BTI aging effect on soft error rate of combination circuit

Liyi Xiao, Zhigang Mao, Chunhua Qi, 2017, 2017 Prognostics and System Health Management Conference (PHM-Harbin).

A clock-less transceiver for global interconnect

Xu Wang, Zhigang Mao, Weiguang Sheng, 2011, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip.

A Novel PTS Technique with Combinative Optimization in Real Part and Imaginary Part for PAPR Reduction in OFDM Systems

Bin Zhou, Zhigang Mao, Jinxiang Wang, 2009, 2009 Third International Conference on Next Generation Mobile Applications, Services and Technologies.

Implementation of Java card Virtual Machine

Zhigang Mao, Yizheng Ye, Liu Songyan, 2008, Journal of Computer Science and Technology.

Conjugate Interleaved Partitioning PTS Scheme for PAPR Reduction of OFDM Signals

Zhigang Mao, Jinxiang Wang, Xin-chun Wu, 2010, Circuits Syst. Signal Process..

Efficient temporal task partition for coarse-grain reconfigurable systems based on Simulated Annealing Genetic Algorithm

Zhigang Mao, Weiguang Sheng, Yifan Zhou, 2011, 2011 9th IEEE International Conference on ASIC.

Link-load balance aware mapping and routing for NoC

Zhigang Mao, Yan Zhang, Zhou Wenbiao, 2007 .

Efficient time-domain residual ISI cancellation for OFDM-based WLAN systems

Wei Zhong, Zhigang Mao, 2006, IEEE Transactions on Consumer Electronics.

A 12-bit 4928 × 3264 pixel CMOS image signal processor for digital still cameras

Wei Jin, Guanghui He, Zhigang Mao, 2017, Integr..

Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm

Liyi Xiao, Zhigang Mao, Weiguang Sheng, 2009, 2009 46th ACM/IEEE Design Automation Conference.

Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture

Zhigang Mao, Weiguang Sheng, Jianfei Jiang, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture

Zhigang Mao, Weiguang Sheng, Jianfei Jiang, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

MEDAC: A Metastability Condition Detection and Correction Technique for a Near-Threshold-Voltage Multi-Voltage-/Frequency-Domain Network-on-Chip

Zhigang Mao, Mingoo Seok, Pavan Kumar Chundi, 2021, IEEE Journal of Solid-State Circuits.

A Mapping Method for Reconfigurable Array based on Decoupled DataFlow

Zhigang Mao, Weiguang Sheng, Jianfei Jiang, 2021, 2021 7th IEEE Intl Conference on Big Data Security on Cloud (BigDataSecurity), IEEE Intl Conference on High Performance and Smart Computing, (HPSC) and IEEE Intl Conference on Intelligent Data and Security (IDS).

Metallic-CN-Removal-Tolerant High-Yield Six-CN-MOSFET SRAM Cell for Carbon-Based Embedded Memory

Zhigang Mao, Volkan Kursun, Hailong Jiao, 2018, IEEE Transactions on Electron Devices.

A cost effective 2-D adaptive block size IDCT architecture for HEVC standard

Zhigang Mao, Weifeng He, Liang Hong, 2013 .