Krishnan Sundaresan

发表

The performance advantage of applying compression to the memory system

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, 2002, MSP/ISMM.

Code compression techniques for embedded systems and their effectiveness

Nihar R. Mahapatra, Krishnan Sundaresan, 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

Accurate energy dissipation and thermal modeling for nanometer-scale buses

Nihar R. Mahapatra, Krishnan Sundaresan, 2005, 11th International Symposium on High-Performance Computer Architecture.

Hardware-only compression to reduce cost and improve utilization of address buses

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

An accurate energy and thermal model for global signal buses

Nihar R. Mahapatra, Krishnan Sundaresan, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Dynamic address compression schemes: a performance, energy, and cost study

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

A Limit Study on the Potential of Compression for Improving Memory System Performance, Power Consumption, and Cost

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, 2005, J. Instr. Level Parallelism.

Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, 2006, GLSVLSI '06.

Energy-efficient compressed address transmission

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Value-Based Bit Ordering for Energy Optimization of On-Chip Global Signal Buses

Nihar R. Mahapatra, Krishnan Sundaresan, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Hardware-only compression of underutilized address buses: design and performance, power, and cost analysis

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, 2003, Proceedings 21st International Conference on Computer Design.

Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, 2006, 2006 International Conference on Computer Design.

Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses

Nihar R. Mahapatra, Krishnan Sundaresan, N. Mahapatra, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

The potential of compression to improve memory system performance, power consumption, and cost

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, 2003, Conference Proceedings of the 2003 IEEE International Performance, Computing, and Communications Conference, 2003..

An Analysis of Timing Violations Due to Spatially Distributed Thermal Effects in Global Wires

Nihar R. Mahapatra, Krishnan Sundaresan, 2007, 2007 44th ACM/IEEE Design Automation Conference.

The performance advantage of applying compression to the memory system

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, 2002, MSP '02.