Sang-Bo Lee

Low-voltage, high-speed circuit designs for gigabit DRAMs

Seung-Moon Yoo, Soo-In Cho, Jai-Hoon Sim, 1997, IEEE J. Solid State Circuits.

A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth

Seung-Moon Yoo, Kinam Kim, Soo-In Cho, 1996, IEEE J. Solid State Circuits.

A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system

Hyoungsik Nam, Hyun-Jun Yoon, Churoo Park, 1998, IEEE J. Solid State Circuits.