B.-S. Moon

Low-voltage, high-speed circuit designs for gigabit DRAMs

Seung-Moon Yoo, Soo-In Cho, Jai-Hoon Sim, 1997, IEEE J. Solid State Circuits.

A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth

Seung-Moon Yoo, Kinam Kim, Soo-In Cho, 1996, IEEE J. Solid State Circuits.

A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface

L. Portmann, J.-S. Kim, S.-B. Cho, 1999, IEEE J. Solid State Circuits.

A 2.5 V, 2.0 GByte/s packet-based SDRAM with a 1.0 Gbps/pin interface

B.-S. Moon, J.-W. Chai, S.-M. Yim, 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).