Jei-Hwan Yoo

Low-voltage, high-speed circuit designs for gigabit DRAMs

Seung-Moon Yoo, Soo-In Cho, Jai-Hoon Sim, 1997, IEEE J. Solid State Circuits.

A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth

Qi Wang, Jaewhan Kim, Jinyoung Kim, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW

Ki-Whan Song, Young-Hyun Jun, Jaewhan Kim, 2011, 2011 IEEE International Solid-State Circuits Conference.

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

Young-Hyun Jun, Dukha Park, Sooho Cha, 2009, IEEE Journal of Solid-State Circuits.

A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth

Seung-Moon Yoo, Kinam Kim, Soo-In Cho, 1996, IEEE J. Solid State Circuits.

8Gb 3D DDR3 DRAM using through-silicon-via technology

So-Ra Kim, Hoon Lee, Tae-Kyung Jung, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 31 ns Random Cycle VCAT-Based 4F $^{2}$ DRAM With Manufacturability and Enhanced Cell Efficiency

Ki-Whan Song, Young-Hyun Jun, Jinyoung Kim, 2010, IEEE Journal of Solid-State Circuits.