Soo-In Cho

Low-voltage, high-speed circuit designs for gigabit DRAMs

Seung-Moon Yoo, Soo-In Cho, Jai-Hoon Sim, 1997, IEEE J. Solid State Circuits.

A 1.2 Gbps CMOS DFE receiver with the extended sampling time window for application to the SSTL channel

Hong-June Park, Soo-In Cho, Young-Soo Sohn, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

A 1-Gb/s bidirectional I/O buffer using the current-mode scheme

Jae-Yoon Sim, Hong-June Park, Soo-In Cho, 1999 .

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

Woo-Jin Lee, Young-Hyun Jun, Jeong-Don Ihm, 2008, IEEE Journal of Solid-State Circuits.

A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth

Seung-Moon Yoo, Kinam Kim, Soo-In Cho, 1996, IEEE J. Solid State Circuits.

A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces

Young-Hyun Jun, Lee-Sup Kim, Soo-In Cho, 2009, IEEE Journal of Solid-State Circuits.