L. Arditi

S.v.p a Toolbox for Speciication and Veriication of Processors

L. Arditi, Jacques Chazarain, 2007 .

A Bit-Vector Algebra for Binary Moment Diagrams

L. Arditi, 2007 .

Esterel as Modeling Languages for the Semi-Formal Validation of a DSP System

L. Leblanc, L. Arditi, H. Boufaïed, 1998 .

Formal Veriication of the Torch Microprocessor Rtl Design

D. Dill, L. Arditi, Satyaki Das, 1998 .

A Framework for Systematic Speciication and Eecient Veriication of Processors

L. Arditi, 2022 .

Coverage Directed Generation of System-Level Test Cases for the Validation of a DSP System

Laurent Arditi, Hédi Boufaïed, Arnaud Cavanié, 2001, FME.

A semi-formal methodology for the functional validation of an industrial DSP system

L. Arditi, G. Clave, L. Arditi, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

Software modeling of a DSP-based architecture using Esterel and UML methodologies to improve validation and enable formal verification

L. Leblanc, L. Arditi, G. Clave, 2000 .

Late Design Changes (ECOs) for Sequentially Optimized Esterel Designs

Michael Kishinevsky, Gérard Berry, Laurent Arditi, 2004, FMCAD.

Late Design Changes ( ECOs ) for Sequentially Optimized High-Level Esterel Designs

L. Arditi, 2004 .

BMDs Can Delay the Use of Theorem Proving for Verifying Arithmetic Assembly Instructions

Laurent Arditi, L. Arditi, 1996, FMCAD.