Nobuaki Otsuka

A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-ß-ratio Memory Cell

Atsushi Kawasumi, Osamu Hirabayashi, Yasuhisa Takeyama, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

DFT techniques for wafer-level at-speed testing of high-speed SRAMs

Atsushi Kawasumi, Osamu Hirabayashi, Yasuhisa Takeyama, 2002, Proceedings. International Test Conference.

A 0.13 µm CMOS Bluetooth EDR Transceiver with High Sensitivity over Wide Temperature Range and Immunity to Process Variation

Makoto Arai, Hiroyuki Kobayashi, Nobuyuki Itoh, 2010, IEICE Trans. Electron..

Bus architecture for 600-MHz 4.5-Mb DDR SRAM

T. Kobayashi, Atsushi Kawasumi, Osamu Hirabayashi, 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications

Atsushi Suzuki, Shinji Miyano, Hiroyuki Takenaka, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Direct Cell-Stability Test Techniques for an SRAM Macro with Asymmetric Cell-Bias-Voltage Modulation

Osamu Hirabayashi, Yasuhisa Takeyama, Keiichi Kushida, 2008, 2008 IEEE International Test Conference.

ELECTRICAL FUSE OF

Katsumi Hisano, Takahiko Sasaki, Nobuaki Otsuka, 2005 .

DFT techniques for memory macro with built-in ECC

Osamu Hirabayashi, Yasuhisa Takeyama, Keiichi Kushida, 2005, 2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05).

An RF MEMS Variable Capacitor with Intelligent Bipolar Actuation

Atsushi Suzuki, Shinji Miyano, Nobuaki Otsuka, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.