Nihar R. Mahapatra

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Efficient techniques based on gate triggering for designing static CMOS ICs with very low glitch power dissipation

Nihar R. Mahapatra, Sriram V. Garimella, Alwin Takeen, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

The performance advantage of applying compression to the memory system

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, 2002, MSP/ISMM.

Node covering, error correcting codes and multiprocessors with very high average fault tolerance

Shantanu Dutt, Nihar R. Mahapatra, S. Dutt, 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing. Digest of Papers.

Sequential and Parallel Branch-and-Bound Search under Limited-Memory Constraints

Shantanu Dutt, Nihar R. Mahapatra, 1999 .

Ethical Considerations in AI-Based Recruitment

Nihar R. Mahapatra, Dena F. Mujtaba, N. Mahapatra, 2019, 2019 IEEE International Symposium on Technology and Society (ISTAS).

Random seeking: a general, efficient, and informed randomized scheme for dynamic load balancing

Shantanu Dutt, Nihar R. Mahapatra, S. Dutt, 1996, Proceedings of International Conference on Parallel Processing.

Towards Natural Language Understanding of Procedural Text Using Recipes

Nihar R. Mahapatra, Dena F. Mujtaba, N. Mahapatra, 2020 .

Analysis of Recent Trends in Automatic Object Identification

Nihar R. Mahapatra, Xavier Williams, 2019, 2019 International Conference on Computational Science and Computational Intelligence (CSCI).

The processor-memory bottleneck: problems and solutions

Nihar R. Mahapatra, Balakrishna Venkatrao, Balakrishna V. Venkatrao, 1999, CROS.

Hardware-efficient and highly-reconfigurable 4- and 2-track fault-tolerant designs for mesh-connected multicomputers

Shantanu Dutt, Nihar R. Mahapatra, S. Dutt, 1996, Proceedings of Annual Symposium on Fault Tolerant Computing.

Code compression techniques for embedded systems and their effectiveness

Nihar R. Mahapatra, Krishnan Sundaresan, 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

Accurate energy dissipation and thermal modeling for nanometer-scale buses

Nihar R. Mahapatra, Krishnan Sundaresan, 2005, 11th International Symposium on High-Performance Computer Architecture.

Interconnect system compression analysis for multi-core architectures

Nihar R. Mahapatra, Jiangjiang Liu, Jianyong Zhang, 2010, 23rd IEEE International SOC Conference.

External Particle-Induced X-Ray Emission Analysis of Medicinal Plant Leaves and Fly Ash

Nihar R. Mahapatra, Santosh S. Teerthe, Mohanraj Pattar, 2014 .

Dynamic User-Driven Available-Memory Non-Minimal Cost-Bounded Search

Nihar R. Mahapatra, Sandeep K. Namilikonda, 2009, IICAI.

New Anticipatory Load Balancing Strategies for Parallel A* Algorithms

Shantanu Dutt, Nihar R. Mahapatra, 1994, Parallel Processing of Discrete Optimization Problems.

Analysis and design of soft-error hardened latches

Nihar R. Mahapatra, Srivathsan Krishnamohan, N. Mahapatra, 2005, ACM Great Lakes Symposium on VLSI.

A Comparative Assessment of Predictive Accuracies of Conventional and Machine Learning Scoring Functions for Protein-Ligand Binding Affinity Prediction

Nihar R. Mahapatra, Hossam M. Ashtawy, N. Mahapatra, 2012, IEEE/ACM Transactions on Computational Biology and Bioinformatics.

A Comparative Assessment of Conventional and Machine-Learning-Based Scoring Functions in Predicting Binding Affinities of Protein-Ligand Complexes

Nihar R. Mahapatra, Hossam M. Ashtawy, 2011, 2011 IEEE International Conference on Bioinformatics and Biomedicine.

Molecular Docking for Drug Discovery: Machine-Learning Approaches for Native Pose Prediction of Protein-Ligand Complexes

Nihar R. Mahapatra, Hossam M. Ashtawy, N. Mahapatra, 2013, CIBB.

Adaptive Quality Equalizing: High-performance load balancing for parallel branch-and-bound across applications and computing systems

Shantanu Dutt, Nihar R. Mahapatra, 2004, Parallel Comput..

Hardware-only compression to reduce cost and improve utilization of address buses

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

Memory system compression and its benefits

Nihar R. Mahapatra, Jiangjiang Liu, Balakrishna Venkatrao, 2002, 15th Annual IEEE International ASIC/SOC Conference.

Energy-optimal signaling and ordering of bits for area-constrained interconnects

Nihar R. Mahapatra, Sharath Jayaprakash, N. Mahapatra, 2008, 2008 IEEE International SOC Conference.

Random Seeking: A General, Efficient, and Informed Randomized Scheme for Dynamic Load Balancing

Shantanu Dutt, Nihar R. Mahapatra, 2000, Int. J. Found. Comput. Sci..

Does Accurate Scoring of Ligands against Protein Targets Mean Accurate Ranking?

Nihar R. Mahapatra, Hossam M. Ashtawy, 2013, ISBRA.

An analysis of the robustness of CMOS delay elements

Nihar R. Mahapatra, Srivathsan Krishnamohan, 2005, GLSVLSI '05.

Analysis of Affordance Detection Methods for Real-World Robotic Manipulation

Nihar R. Mahapatra, Xavier Williams, 2019, 2019 9th International Symposium on Embedded Computing and System Design (ISED).

Elemental Analysis of Ancient Gold and Silver Coins Using Nuclear Techniques

Nihar R. Mahapatra, V. Vijayan, T. R. Rautray, 2014 .

An accurate energy and thermal model for global signal buses

Nihar R. Mahapatra, Krishnan Sundaresan, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

A Quantitative Evaluation of Limited-Memory Branch-and-Bound Algorithms

Nihar R. Mahapatra, Douglas E. Covelli, Yuval Beres, 1999, IC-AI.

Modeling the Automation Level of Cyber-Physical Systems Designed for Food Preparation

Nihar R. Mahapatra, Dena F. Mujtaba, N. Mahapatra, 2019, 2019 9th International Symposium on Embedded Computing and System Design (ISED).

Increasing the energy efficiency of pipelined circuits via slack redistribution

Nihar R. Mahapatra, Srivathsan Krishnamohan, 2005, GLSVLSI '05.

Partitioned reuse cache for energy-efficient soft-error protection of functional units

Nihar R. Mahapatra, Kaushal R. Gandhi, N. Mahapatra, 2008, 2008 IEEE International SOC Conference.

Dynamic address compression schemes: a performance, energy, and cost study

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

Machine-learning scoring functions for identifying native poses of ligands docked to known and novel proteins

Nihar R. Mahapatra, Hossam M. Ashtawy, N. Mahapatra, 2015, BMC Bioinformatics.

Slack redistribution in pipelined circuits for enhanced soft-error rate reduction

Nihar R. Mahapatra, Srivathsan Krishnamohan, 2008, 2008 IEEE International SOC Conference.

Adaptive quality equalizing: high-performance load balancing for parallel branch-and bound across applications and computing systems

Shantanu Dutt, Nihar R. Mahapatra, S. Dutt, 2002, Proceedings of the First Merged International Parallel Processing Symposium and Symposium on Parallel and Distributed Processing.

Exploiting Data-Dependent Slack Using Dynamic Multi-VDD to Minimize Energy Consumption in Datapath Circuits

Nihar R. Mahapatra, Kaushal R. Gandhi, 2006, Proceedings of the Design Automation & Test in Europe Conference.

A study of hardware techniques that dynamically exploit frequent operands to reduce power consumption in integer function units

Nihar R. Mahapatra, Kaushal R. Gandhi, N. Mahapatra, 2003, Proceedings 21st International Conference on Computer Design.

Enhancing Available-Memory Cost-Bounded Iterative-Deepening Search

Nihar R. Mahapatra, Sandeep K. Namilikonda, 2008, IC-AI.

A Comparative Assessment of Ranking Accuracies of Conventional and Machine-Learning-Based Scoring Functions for Protein-Ligand Binding Affinity Prediction

Nihar R. Mahapatra, Hossam M. Ashtawy, 2012, IEEE/ACM Transactions on Computational Biology and Bioinformatics.

Energy-Efficient Soft-Error Protection Using Operand Encoding and Operation Bypass

Nihar R. Mahapatra, Kaushal R. Gandhi, 2008, 21st International Conference on VLSI Design (VLSID 2008).

A Limit Study on the Potential of Compression for Improving Memory System Performance, Power Consumption, and Cost

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, 2005, J. Instr. Level Parallelism.

Enabling Affordance-Guided Grasp Synthesis for Robotic Manipulation

Nihar R. Mahapatra, Xavier Williams, N. Mahapatra, 2020 .

Dynamically exploiting frequent operand values for energy efficiency in integer functional units

Nihar R. Mahapatra, Kaushal R. Gandhi, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Combining error masking and error detection plus recovery to combat soft errors in static CMOS circuits

Nihar R. Mahapatra, Srivathsan Krishnamohan, N. Mahapatra, 2005, 2005 International Conference on Dependable Systems and Networks (DSN'05).

Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, 2006, GLSVLSI '06.

Scalable Global and Local Hashing Strategies for Duplicate Pruning in Parallel A* Graph Search

Shantanu Dutt, Nihar R. Mahapatra, S. Dutt, 1997, IEEE Trans. Parallel Distributed Syst..

Energy-efficient compressed address transmission

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

An empirical and analytical comparison of delay elements and a new delay element design

Nihar R. Mahapatra, S. V. Garimella, Alwin Tareen, 2000, Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era.

Value-Based Bit Ordering for Energy Optimization of On-Chip Global Signal Buses

Nihar R. Mahapatra, Krishnan Sundaresan, 2006, Proceedings of the Design Automation & Test in Europe Conference.

An efficient delay-optimal distributed termination detection algorithm

Shantanu Dutt, Nihar R. Mahapatra, S. Dutt, 2007, J. Parallel Distributed Comput..

BgN-Score and BsN-Score: Bagging and boosting based ensemble neural networks scoring functions for accurate binding affinity prediction of protein-ligand complexes

Nihar R. Mahapatra, Hossam M. Ashtawy, N. Mahapatra, 2015, BMC Bioinformatics.

Boosted neural networks scoring functions for accurate ligand docking and ranking

Nihar R. Mahapatra, Hossam M. Ashtawy, N. Mahapatra, 2018, J. Bioinform. Comput. Biol..

Hardware-only compression of underutilized address buses: design and performance, power, and cost analysis

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, 2003, Proceedings 21st International Conference on Computer Design.

An Instance-Based Learning Approach for Available-Memory Non-minimal Cost-Bounded Search

Nihar R. Mahapatra, Sandeep K. Namilikonda, 2009, 2009 International Conference on Machine Learning and Applications.

Energy-Efficient Encoding for High-Performance Buses with Staggered Repeaters

Nihar R. Mahapatra, Sharath Jayaprakash, 2009, 2009 IEEE Computer Society Annual Symposium on VLSI.

Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor Buses

Nihar R. Mahapatra, Sharath Jayaprakash, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

Hardware-Efficient and Highly Reconfigurable 4- and 2-Track Fault-Tolerant Designs for Mesh-Connected Arrays

Shantanu Dutt, Nihar R. Mahapatra, S. Dutt, 2001, J. Parallel Distributed Comput..

Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, 2006, 2006 International Conference on Computer Design.

An efficient error-masking technique for improving the soft-error robustness of static CMOS circuits

Nihar R. Mahapatra, Srivathsan Krishnamohan, N. Mahapatra, 2004, IEEE International SOC Conference, 2004. Proceedings..

Comparison and analysis of delay elements

Nihar R. Mahapatra, S. V. Garimella, A. Tareen, 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

Information pattern aware design strategies for nanometer-scale address buses

Nihar R. Mahapatra, Jiangjiang Liu, 2004 .

Efficient network-flow based techniques for dynamic fault reconfiguration in FPGAs

Shantanu Dutt, Nihar R. Mahapatra, 1999, Digest of Papers. Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing (Cat. No.99CB36352).

Node-Covering, Error-Correcting Codes and Multiprocessors with Very High Average Fault Tolerance

Shantanu Dutt, Nihar R. Mahapatra, 1997, IEEE Trans. Computers.

A highly-efficient technique for reducing soft errors in static CMOS circuits

Nihar R. Mahapatra, Srivathsan Krishnamohan, N. Mahapatra, 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses

Nihar R. Mahapatra, Krishnan Sundaresan, N. Mahapatra, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

The potential of compression to improve memory system performance, power consumption, and cost

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, 2003, Conference Proceedings of the 2003 IEEE International Performance, Computing, and Communications Conference, 2003..

Message from the technical program chairs

Nihar R. Mahapatra, Pramod Kumar Meher, Vinod A. Prasad, 2011 .

The role of computer technology trends in computer architecture education

Nihar R. Mahapatra, Alwin Tareen, 1999, WCAE-5 '99.

The role of interconnects in the performance scalability of multicore architectures

Nihar R. Mahapatra, Jiangjiang Liu, 2008, 2008 IEEE International SOC Conference.

Scalable duplicate pruning strategies for parallel A* graph search

Shantanu Dutt, Nihar R. Mahapatra, S. Dutt, 1993, Proceedings of 1993 5th IEEE Symposium on Parallel and Distributed Processing.

An Analysis of Timing Violations Due to Spatially Distributed Thermal Effects in Global Wires

Nihar R. Mahapatra, Krishnan Sundaresan, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Efficient techniques for modeling and mitigation of soft errors in nanometer-scale static cmos logic circuits

Nihar R. Mahapatra, Srivathsan Krishnamohan, 2005 .

Scalable Load Balancing Strategies for Parallel A* Algorithms

Shantanu Dutt, Nihar R. Mahapatra, S. Dutt, 1994, J. Parallel Distributed Comput..

Multi-objective optimization of item selection in computerized adaptive testing

Nihar R. Mahapatra, Dena F. Mujtaba, 2021, GECCO.

The performance advantage of applying compression to the memory system

Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan, 2002, MSP '02.

Gate triggering: a new framework for minimizing glitch power dissipation in static CMOS ICs and its ILP-based optimization

Nihar R. Mahapatra, R. Janakiraman, N. Mahapatra, 2000, Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474).