R. Ohba

发表

Non-volatile Si quantum memory with self-aligned doubly-stacked dots

Ken Uchida, Akira Toriumi, Junji Koga, 2000 .

Analytical Single-Electron Transistor(SET)Model for Design and Analysis of Realistic SET Circuits

K. Matsuzawa, S. Takagi, K. Uchida, 2000 .

Experimental study of nonstationary electron transport in sub-0.1 μm metal–oxide–silicon devices: Velocity overshoot and its degradation mechanism

T. Mizuno, R. Ohba, 1997 .

Experimental evidences of quantum-mechanical effects on low-field mobility, gate-channel capacitance, and threshold voltage of ultrathin body SOI MOSFETs

T. Numata, S. Takagi, K. Uchida, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Nonvolatile Memories Using Single Electron Tunneling Effects in Si Quantum Dots Inside Tunnel Silicon Oxide

R. Ohba, 2014 .

Non-volatile Si quantum memory with self-aligned doubly-stacked dots

N. Sugiyama, A. Toriumi, J. Koga, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Programmable single-electron transistor logic for future low-power intelligent LSI: proposal and room-temperature operation

Ken Uchida, Akira Toriumi, Junji Koga, 2003 .

Single-electron random-number generator (RNG) for highly secure ubiquitous computing applications

K. Uchida, S. Fujita, T. Tanamoto, 2002, Digest. International Electron Devices Meeting,.

Velocity overshoot greater than 107 cm/s at room temperature in sub‐0.1‐μm silicon‐on‐insulator devices

K. Ohuchi, T. Mizuno, R. Ohba, 1996 .

Nonstationary electron/hole transport in sub-0.1 /spl mu/m MOS devices: correlation with mobility and low-power CMOS application

Ryuji Ohba, T. Mizuno, R. Ohba, 2001 .

Experimental study of carrier velocity overshoot in sub-0.1 /spl mu/m devices-physical limitation of MOS structures

T. Mizuno, R. Ohba, 1996, International Electron Devices Meeting. Technical Digest.

1200μm2 Physical Random-Number Generators Based on SiN MOSFET for Secure Smart-Card Application

Shinobu Fujita, Tetsufumi Tanamoto, Mari Matsumoto, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Physical random number generator based on MOS structure after soft breakdown

R. Ohba, K. Uchida, S. Fujita, 2004, IEEE Journal of Solid-State Circuits.

10 nm bulk-planar SONOS-type memory with double tunnel junction and sub-10 nm scaling utilizing source to drain direct tunnel sub-threshold

S. Fujita, Y. Mitani, R. Ohba, 2008, 2008 IEEE International Electron Devices Meeting.

Influence of Channel Depletion on the Carrier Charging Characteristics in Si Nanocrystal Floating Gate Memory

Ken Uchida, Akira Toriumi, Junji Koga, 2000 .

35 nm floating gate planar MOSFET memory using double junction tunneling

N. Sugiyama, S. Fujita, Y. Mitani, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..