C. Goutis

发表

A Low-Power Design Methodology / Flow and its Application to the Implementation of a DCS 1800-GSM / DECT Modulator / Demodulator ( ESPRIT 25256 ) Title : Low Power Methodology for Designing Multiple Filters

S. Nikolaidis, K. Masselos, C. Goutis, 2022 .

Combined Application of Low Power Code Transformations and Sub-word Parallelism Exploitation for VLIW Multi-media Processors

F. Catthoor, K. Masselos, C. Goutis, 2022 .

Resource aware mapping on coarse grained reconfigurable arrays

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2009, Microprocess. Microsystems.

A novel methodology for power consumption reduction in a class of DSP algorithms

Thanos Stouraitis, Kostas Masselos, Constantinos E. Goutis, 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

Array processor for LS FIR system identification

Constantinos E. Goutis, Spiridon Nikolaidis, Sergios Theodoridis, 1991 .

Chinese Remainder Theorem-based Algorithm for Convolution

Thanos Stouraitis, Gauthier Lafruit, Jan Cornelis, 1995 .

Novel vector quantization based algorithms for low-power image coding and decoding

T. Stouraitis, K. Masselos, C. Goutis, 1999 .

A methodology for speeding up edge and line detection algorithms focusing on memory architecture utilization

Vasilios I. Kelefouras, C. Goutis, A. Kritikakou, 2014, The Journal of Supercomputing.

A data locality methodology for matrix–matrix multiplication algorithm

Nikolaos S. Alachiotis, Vasilios I. Kelefouras, C. Goutis, 2012, The Journal of Supercomputing.

A Systematic Flow for Developing Totally Self-Checking Architectures for SHA-1 and SHA-2 Cryptographic Hash Families

George Athanasiou, George Theodoridis, Constantinos E. Goutis, 2013, J. Circuits Syst. Comput..

Prime-factor DCT algorithms

Thanos Stouraitis, Constantinos E. Goutis, Chrissavgi Dre, 1995, IEEE Trans. Signal Process..

A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems

Michalis D. Galanis, Constantinos E. Goutis, Athanasios Kakarountas, 2006, Microelectron. J..

A partitioning methodology for accelerating applications in hybrid reconfigurable platforms

Dimitrios Soudris, Michalis D. Galanis, George Theodoridis, 2005, Design, Automation and Test in Europe.

A systematic approach to classify design-time global scheduling techniques

Francky Catthoor, Constantinos E. Goutis, Vasilios I. Kelefouras, 2013, CSUR.

Design and implementation of totally-self checking SHA-1 and SHA-256 hash functions' architectures

George Athanasiou, George Theodoridis, Constantinos E. Goutis, 2016, Microprocess. Microsystems.

Hardware implementation of the Totally Self-Checking SHA-256 hash core

George Athanasiou, Constantinos E. Goutis, Athanasios Kakarountas, 2015, IEEE EUROCON 2015 - International Conference on Computer as a Tool (EUROCON).

Efficient implementation of the keyed-hash message authentication code (HMAC) using the SHA-1 hash function

Constantinos E. Goutis, Athanasios Kakarountas, Harris E. Michail, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

A methodology for partitioning DSP applications in hybrid reconfigurable systems

Dimitrios Soudris, Michalis D. Galanis, George Theodoridis, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A framework for partitioning computational intensive applications in hybrid reconfigurable platforms

Dimitrios Soudris, Michalis D. Galanis, George Theodoridis, 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications

Francky Catthoor, Michalis D. Galanis, George Theodoridis, 2004, SCOPES.

A Framework for Data Partitioning for C++ Data-Intensive Applications

Francky Catthoor, Michalis D. Galanis, George Theodoridis, 2004, Des. Autom. Embed. Syst..

On the Design of Two-Level Pipelined Processor Arrays

Vassilis Paliouras, Thanos Stouraitis, Dimitrios Soudris, 1993 .

Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path

Gregory Dimitroulakos, Costas E. Goutis, Michalis D. Galanis, 2008, J. Signal Process. Syst..

Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.

A methodology for speeding up matrix vector multiplication for single/multi-core architectures

Constantinos E. Goutis, Vasilios I. Kelefouras, Angeliki Kritikakou, 2015, The Journal of Supercomputing.

A methodology for speeding up loop kernels by exploiting the software information and the memory architecture

Constantinos E. Goutis, Vasilios I. Kelefouras, Angeliki Kritikakou, 2015, Comput. Lang. Syst. Struct..

A Methodology for Speeding up MVM for Regular, Toeplitz and Bisymmetric Toeplitz Matrices

Constantinos E. Goutis, Vasilios I. Kelefouras, Angeliki Kritikakou, 2014, J. Signal Process. Syst..

A Matrix–Matrix Multiplication methodology for single/multi-core architectures using SIMD

Constantinos E. Goutis, Vasilios I. Kelefouras, Angeliki Kritikakou, 2014, The Journal of Supercomputing.

A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization

George Athanasiou, Constantinos E. Goutis, Nikolaos S. Alachiotis, 2011, IEEE Transactions on Signal Processing.

A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints

Hugo De Man, Francky Catthoor, Constantinos E. Goutis, 2000, J. VLSI Signal Process..

Speedups in embedded systems with a high-performance coprocessor datapath

Spyros Tragoudas, Michalis D. Galanis, Constantinos E. Goutis, 2007, TODE.

CMOS multi-input gate implementations for low-power digital design

Constantinos E. Goutis, Odysseas Koufopavlou, L. Bisdounis, 1995 .

On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs

George Athanasiou, George Theodoridis, Constantinos E. Goutis, 2014, Integr..

Optimising the SHA-512 cryptographic hash function on FPGAs

George Athanasiou, George Theodoridis, Constantinos E. Goutis, 2013, IET Comput. Digit. Tech..

On the exploitation of a high-throughput SHA-256 FPGA design for HMAC

Vasilios I. Kelefouras, HARRIS E. MICHAIL, GEORGE S. ATHANASIOU, 2012, TRETS.

A Top-Down Design Methodology for Ultrahigh-Performance Hashing Cores

Constantinos E. Goutis, Athanasios Kakarountas, Harris E. Michail, 2009, IEEE Transactions on Dependable and Secure Computing.

Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2009, The Journal of Supercomputing.

A unified evaluation framework for coarse grained reconfigurable array architectures

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2007, CF '07.

Design space exploration of an optimized compiler approach for a generic reconfigurable array architecture

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2007, The Journal of Supercomputing.

Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.

Non-linear optimization: artificial neural network solution techniques applied to the optimum linear feedback control of linear discrete-time dynamic systems

George-Peter K. Economou, T. Stouraitis, C. Goutis, 1994, Proceedings of Twentieth Euromicro Conference. System Architecture and Integration.

A code transformation-based methodology for improving I-cache performance of DSP applications

Dimitrios Soudris, Constantinos E. Goutis, N. Liveris, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

A code transformation-based methodology for improving I-cache performance

Dimitrios Soudris, Constantinos E. Goutis, Nikolaos D. Zervas, 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

Effect of data transfer and storage optimization on design quality factors of multimedia algorithms realized on instruction set processors

Francky Catthoor, Kostas Masselos, Constantinos E. Goutis, 2001 .

A floating-point advanced cordic processor

D. E. METAFAS, C. E. GOUTIS, C. Goutis, 1995, J. VLSI Signal Process..

Implementation of Given's Rotation processors for DSP real-time applications

Constantinos E. Goutis, Spiridon Nikolaidis, D. E. Metafas, 1993, Microprocess. Microprogramming.

VLSI design of an 8-bit fixed point CORDIC processor with extended operation set

D.E. Metafas, G.A. Krikis, C.E. Goutis, 1991, Euro ASIC '91.

Performance Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path

Michalis D. Galanis, Constantinos E. Goutis, Grigoris Dimitroulakos, 2006, 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation.

A high-performance data path for synthesizing DSP kernels

Spyros Tragoudas, Michalis D. Galanis, George Theodoridis, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels

Spyros Tragoudas, Michalis D. Galanis, George Theodoridis, 2005, J. Circuits Syst. Comput..

Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path

Spyros Tragoudas, Dimitrios Soudris, Michalis D. Galanis, 2004, PATMOS.

Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path

Spyros Tragoudas, Dimitrios Soudris, Michalis D. Galanis, 2004, FPL.

A Novel Data-Path for Accelerating DSP Kernels

Spyros Tragoudas, Dimitrios Soudris, Michalis D. Galanis, 2004, SAMOS.

Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints

George Athanasiou, Francky Catthoor, Constantinos E. Goutis, 2013, TACO.

Low-power implementation of discrete wavelet transform

Thanos Stouraitis, Constantinos E. Goutis, Kostas Masselos, 1998, 9th European Signal Processing Conference (EUSIPCO 1998).

Low power architectures for digital signal processing

Thanos Stouraitis, Constantinos E. Goutis, Kostas Masselos, 2000, J. Syst. Archit..