M. Natsui

发表

Design of a 270ps-access 7-transistor/2-magnetic-tunnel-junction cell circuit for a high-speed-search nonvolatile ternary content-addressable memory

Tetsuo Endoh, Takahiro Hanyu, Shoun Matsunaga, 2012 .

Design of a Nine-Transistor/Two-Magnetic-Tunnel-Junction-Cell-Based Low-Energy Nonvolatile Ternary Content-Addressable Memory

H. Ohno, T. Endoh, T. Hanyu, 2012 .

Six-input lookup table circuit with 62% fewer transistors using nonvolatile logic-in-memory architecture with series/parallel-connected magnetic tunnel junctions

H. Ohno, T. Endoh, D. Suzuki, 2012 .

Design of a Current-Mode Linear-Sum-Based Bitcounting Circuit with an MTJ-Based Compensator for Binarized Neural Networks

Takahiro Hanyu, Masanori Natsui, Tomoki Chiba, 2019, 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL).

Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage

T. Nasuno, T. Yoshiduka, M. Yasuhira, 2020, 2020 IEEE Symposium on VLSI Circuits.

First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400°C thermal tolerance by canted SOT structure and its advanced patterning/SOT channel technology

T. Endoh, S. Fukami, S. Ikeda, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition

Yitao Ma, Takahiro Hanyu, Masaaki Niwa, 2020, IEEE Journal of Solid-State Circuits.

A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure

Daisuke Suzuki, Tetsuo Endoh, Takahiro Hanyu, 2014, IEICE Electronics Express.

Cost-Efficient Self-Terminated Write Driver for Spin-Transfer-Torque RAM and Logic

Daisuke Suzuki, Takahiro Hanyu, Masanori Natsui, 2014, IEEE Transactions on Magnetics.

Analysis of single-event upset of magnetic tunnel junction used in spintronic circuits caused by radiation-induced current

H. Ohno, T. Hanyu, M. Natsui, 2014 .

Design and fabrication of a perpendicular magnetic tunnel junction based nonvolatile programmable switch achieving 40% less area using shared-control transistor structure.

Tetsuo Endoh, Takahiro Hanyu, Hiroaki Honjo, 2014, Journal of applied physics.

Design and evaluation of a 67% area-less 64-bit parallel reconfigurable 6-input nonvolatile logic element using domain-wall motion devices

Takahiro Hanyu, Daisuke Suzuki, Masanori Natsui, 2014 .

A 71%-Area-Reduced Six-Input Nonvolatile Lookup-Table Circuit Using a Three-Terminal Magnetic-Tunnel-Junction-Based Single-Ended Structure

Takahiro Hanyu, Daisuke Suzuki, Masanori Natsui, 2013 .

Systematic Intrusion Detection Technique for an In-vehicle Network Based on Time-Series Feature Extraction

Takahiro Hanyu, Masanori Natsui, Hiroki Suda, 2018, 2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL).

Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA

T. Hanyu, M. Natsui, D. Suzuki, 2012, 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS).

Fully parallel 6T-2MTJ nonvolatile TCAM with single-transistor-based self match-line discharge control

Tetsuo Endoh, Takahiro Hanyu, Shoun Matsunaga, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

Fine-Grained Power-Gating Scheme of a Metal–Oxide–Semiconductor and Magnetic-Tunnel-Junction-Hybrid Bit-Serial Ternary Content-Addressable Memory

Tetsuo Endoh, Takahiro Hanyu, Shoun Matsunaga, 2010 .

Design of a Nine-Transistor/Two-Magnetic-Tunnel-Junction-Cell-Based Low-Energy Nonvolatile Ternary Content-Addressable Memory

H. Ohno, T. Endoh, T. Hanyu, 2012 .

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating

Daisuke Suzuki, Shoji Ikeda, Tetsuo Endoh, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing

Daisuke Suzuki, Shoji Ikeda, Hiroki Koike, 2016, Proceedings of the IEEE.

Automated Sizing of Analog Circuits based on Genetic Algorithm with Parameter Orthogonalization Procedure

Yoshiaki Tadokoro, Masanori Natsui, Y. Tadokoro, 2016, ICINCO-ICSO.

Fabrication of a 99%-energy-less nonvolatile multi-functional CAM chip using hierarchical power gating for a massively-parallel full-text-search engine

T. Endoh, S. Fukami, S. Ikeda, 2013, 2013 Symposium on VLSI Technology.

Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme

Shoji Ikeda, Tetsuo Endoh, Takahiro Hanyu, 2012, 17th Asia and South Pacific Design Automation Conference.

12.1 An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz

Daisuke Suzuki, Shoji Ikeda, Hiroki Koike, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing

Daisuke Suzuki, Shoji Ikeda, Tetsuo Endoh, 2015, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor

Daisuke Suzuki, Naoya Onizawa, Takahiro Hanyu, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design

Hiroki Koike, Tetsuo Endoh, Takahiro Hanyu, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure

Daisuke Suzuki, Shoji Ikeda, Tetsuo Endoh, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

Fabrication of a nonvolatile lookup-table circuit chip using magneto/semiconductor-hybrid structure for an immediate-power-up field programmable gate array

Daisuke Suzuki, Shoji Ikeda, Tetsuo Endoh, 2009, 2009 Symposium on VLSI Circuits.

Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology

Takayuki Konishi, Boris Murmann, Jun Gyu Lee, 2011, IEICE Trans. Electron..