Dajiang Zhou

发表

Framework and VLSI Architecture of Measurement-Domain Intra Prediction for Compressively Sensed Visual Contents

Satoshi Goto, Jian-Bin Zhou, Dajiang Zhou, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Chain-NN: An energy-efficient 1D chain architecture for accelerating deep convolutional neural networks

Dajiang Zhou, Takeshi Yoshimura, Shihao Wang, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

A Hardware-Efficient Dual-Standard VLSI Architecture for MC Interpolation in AVS and H.264

Dajiang Zhou, Peilin Liu, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Prioritized reference decision for efficient motion vector coding

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2009, 2009 IEEE International Symposium on Circuits and Systems.

A Low-Cost VLSI Architecture of Multiple-Size IDCT for H.265/HEVC

Satoshi Goto, Dajiang Zhou, Peilin Liu, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design

Satoshi Goto, Jinjia Zhou, Yijin Zhao, 2017, IEEE Journal of Solid-State Circuits.

A 1991 Mpixels/s intra prediction architecture for Super Hi-Vision H.264/AVC encoder

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2012, 2012 Proceedings of the 20th European Signal Processing Conference (EUSIPCO).

A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder

Satoshi Goto, Dajiang Zhou, Peilin Liu, 2010, IEICE Trans. Electron..

D-11-67 Interface Design for FPGA-based Video Decoder

Satoshi Goto, Dajiang Zhou, Yue Pan, 2013 .

A 7-Die 3D Stacked 3840×2160@120 fps Motion Estimation Processor

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2017, IEICE Trans. Electron..

Measurement-domain intra prediction framework for compressively sensed images

Satoshi Goto, Jian-Bin Zhou, Dajiang Zhou, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Fast Prediction Unit Selection and Mode Selection for HEVC Intra Prediction

Satoshi Goto, Dajiang Zhou, Peilin Liu, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Dual-Mode Deblocking Filter Design for HEVC and H.264/AVC

Xiao Peng, Satoshi Goto, Jinjia Zhou, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A 98 GMACs/W 32-core vector processor in 65nm CMOS

Satoshi Goto, Xin Jin, Dajiang Zhou, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding

Satoshi Goto, Dajiang Zhou, Takeshi Yoshimura, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A fixed-complexity HEVC inter mode filtering algorithm based on distribution of IME-FME cost ratio

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Interlaced asymmetric search range assignment for bidirectional motion estimation

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2012, 2012 19th IEEE International Conference on Image Processing.

Fast SAO Estimation Algorithm and Its Implementation for 8K×4K @ 120 FPS HEVC Encoding

Satoshi Goto, Dajiang Zhou, Shinji Kimura, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications

Jinjia Zhou, Jian-Bin Zhou, Dajiang Zhou, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 360Mbin/s CABAC decoder for H.264/AVC level 5.1 applications

Satoshi Goto, Dajiang Zhou, Peilin Liu, 2009, 2009 International SoC Design Conference (ISOCC).

A 1080p@60fps multi-standard video decoder chip designed for power and cost efficiency in a system perspective

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2009, 2009 Symposium on VLSI Circuits.

A new architecture for high performance intra prediction in H.264 decoder

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2009, 2009 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS).

A 115 mW 1 Gbps Bit-Serial Layered LDPC Decoder for WiMAX

Xiao Peng, Satoshi Goto, Dajiang Zhou, 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

VLSI Implementation of HEVC Motion Compensation With Distance Biased Direct Cache Mapping for 8K UHDTV Applications

Satoshi Goto, Jian-Bin Zhou, Dajiang Zhou, 2017, IEEE Transactions on Circuits and Systems for Video Technology.

Transform-based fast mode and depth decision algorithm for HEVC intra prediction

Satoshi Goto, Dajiang Zhou, Gang He, 2013, 2013 IEEE 10th International Conference on ASIC.

A High Performance HEVC De-Blocking Filter and SAO Architecture for UHDTV Decoder

Satoshi Goto, Dajiang Zhou, Jiayi Zhu, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS

Xiao Peng, Satoshi Goto, Dajiang Zhou, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

An Efficient Motion Vector Coding Scheme Based on Prioritized Reference Decision

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering

Xiao Peng, Qian He, Ying Cui, 2011, 2011 IEEE Workshop on Signal Processing Systems (SiPS).

A high-parallelism reconfigurable permutation network for IEEE 802.11n??802.16e LDPC decoder

Xiao Peng, Satoshi Goto, Dajiang Zhou, 2009, 2009 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS).

A combined SAO and de-blocking filter architecture for HEVC video decoder

Satoshi Goto, Dajiang Zhou, Gang He, 2013, 2013 IEEE International Conference on Image Processing.

Accelerating HEVC Inter Prediction with Improved Merge Mode Handling

Dajiang Zhou, Shinji Kimura, Heming Sun, 2017, IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences.

A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2012, 2012 IEEE International Solid-State Circuits Conference.

Reducing power consumption of HEVC codec with lossless reference frame recompression

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2014, 2014 IEEE International Conference on Image Processing (ICIP).

High Profile Intra Prediction Architecture for UHD H.264 Decoder

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2010, IPSJ Trans. Syst. LSI Des. Methodol..

A lossless frame recompression scheme for reducing DRAM power in video encoding

Satoshi Goto, Dajiang Zhou, Xuena Bao, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

A 4320p 60fps H.264/AVC intra-frame encoder chip with 1.41Gbins/s CABAC

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS

Xiao Peng, Satoshi Goto, Dajiang Zhou, 2011, IEEE Asian Solid-State Circuits Conference 2011.

A Variable-Clock-Cycle-Path VLSI Design of Binary Arithmetic Decoder for H.265/HEVC

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2018, IEEE Transactions on Circuits and Systems for Video Technology.

An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder

Satoshi Goto, Dajiang Zhou, Shinji Kimura, 2014, 2014 IEEE Visual Communications and Image Processing Conference.

High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for Ultra-HD HEVC Video Encoding

Yunsong Li, Satoshi Goto, Dajiang Zhou, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An adaptive bandwidth reduction scheme for video coding

Satoshi Goto, Xin Jin, Dajiang Zhou, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

OpenCL based high-quality HEVC motion estimation on GPU

Satoshi Goto, Dajiang Zhou, Fan Wang, 2014, 2014 IEEE International Conference on Image Processing (ICIP).

A 1.59 Gpixel/s Motion Estimation Processor With $-$211 to +211 Search Range for UHDTV Video Encoder

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2014, IEEE Journal of Solid-State Circuits.

Alternating asymmetric search range assignment for bidirectional motion estimation in H.265/HEVC and H.264/AVC

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2014, J. Vis. Commun. Image Represent..

Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA

Dajiang Zhou, Shihao Wang, Shinji Kimura, 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

A 24.5–53.6pJ/pixel 4320p 60fps H.264/AVC intra-frame video encoder chip in 65nm CMOS

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

A 64-cycle-per-MB joint parameter decoder architecture for ultra high definition H.264/AVC applications

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2009, 2009 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS).

Unified Parameter Decoder Architecture for H.265/HEVC Motion Vector and Boundary Strength Decoding

Satoshi Goto, Jian-Bin Zhou, Dajiang Zhou, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An Advanced Hierarchical Motion Estimation Scheme With Lossless Frame Recompression and Early-Level Termination for Beyond High-Definition Video Coding

Satoshi Goto, Dajiang Zhou, Peilin Liu, 2012, IEEE Transactions on Multimedia.

100x Evolution of Video Codec Chips

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2017, ISPD.

A constant rate bandwidth reduction architecture with adaptive compression mode decision for video decoding

Satoshi Goto, Xin Jin, Dajiang Zhou, 2010, 2010 18th European Signal Processing Conference.

VLSI architecture of HEVC intra prediction for 8K UHDTV applications

Satoshi Goto, Jian-Bin Zhou, Dajiang Zhou, 2014, 2014 IEEE International Conference on Image Processing (ICIP).

A 530 Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2011, IEICE Trans. Electron..

Block-pipelining cache for motion compensation in high definition H.264/AVC video decoder

Satoshi Goto, Dajiang Zhou, Peilin Liu, 2009, 2009 IEEE International Symposium on Circuits and Systems.

A Bandwidth Reduction Scheme and Its VLSI Implementation for H.264/AVC Motion Vector Decoding

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2010, PCM.

Ultra low power QC-LDPC decoder with high parallelism

Xiao Peng, Ying Cui, Satoshi Goto, 2011, 2011 IEEE International SOC Conference.

A 16–65 cycles/MB H.264/AVC motion compensation architecture for Quad-HD applications

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2011, 2011 19th European Signal Processing Conference.

Cache Based Motion Compensation Architecture for Quad-HD H.264/AVC Video Decoder

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2011, IEICE Trans. Electron..

Lossy Compression for Embedded Computer Vision Systems

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2018, IEEE Access.

Frame-level quality and memory traffic allocation for lossy embedded compression in video codec systems

Satoshi Goto, Dajiang Zhou, Li Guo, 2016, 2016 IEEE International Conference on Multimedia & Expo Workshops (ICMEW).

Approximate-DCT-derived measurement matrices for compressed sensing

Satoshi Goto, Jian-Bin Zhou, Dajiang Zhou, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

A macro-layer level fully parallel layered LDPC decoder SOC for IEEE 802.15.3c application

Xiao Peng, Satoshi Goto, Dajiang Zhou, 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test.

Low-Complexity Rate-Distortion Optimization Algorithms for HEVC Intra Prediction

Satoshi Goto, Dajiang Zhou, Heming Sun, 2014, MMM.

A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A 1 Gbin/s CABAC encoder for H.264/AVC

Satoshi Goto, Dajiang Zhou, Wei Fei, 2011, 2011 19th European Signal Processing Conference.

Embedded Frame Compression for Energy-Efficient Computer Vision Systems

Jinjia Zhou, Dajiang Zhou, Li Guo, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Hardware-oriented rate-distortion optimization algorithm for HEVC intra-frame encoder

Dajiang Zhou, Shinji Kimura, Heming Sun, 2015, 2015 IEEE International Conference on Multimedia & Expo Workshops (ICMEW).

A 98 GMACs/W 32-Core Vector Processor in 65 nm CMOS

Satoshi Goto, Xin Jin, Dajiang Zhou, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Frame-Parallel 2 Gpixel/s Video Decoder Chip for UHDTV and 3-DTV/FTV Applications

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

HyDMA: low-latency inter-core DMA based on a hybrid packet-circuit switching network-on-chip

Dajiang Zhou, Peilin Liu, Ke Jin, 2016, IEICE Electron. Express.

An optimized MC interpolation architecture for HEVC

Satoshi Goto, Dajiang Zhou, Zhengyan Guo, 2012, 2012 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

Unified VLSI Architecture of Motion Vector and Boundary Strength Parameter Decoder for 8K UHDTV HEVC Decoder

Satoshi Goto, Jian-Bin Zhou, Dajiang Zhou, 2014, PCM.

An SoC based HW/SW co-design architecture for multi-standard audio decoding

Dajiang Zhou, Peilin Liu, Bin He, 2007, 2007 IEEE Asian Solid-State Circuits Conference.

De-blocking Filter Design for HEVC and H.264/AVC

Xiao Peng, Satoshi Goto, Jinjia Zhou, 2012, PCM.

A Bandwidth Optimized, 64 Cycles/MB Joint Parameter Decoder Architecture for Ultra High Definition H.264/AVC Applications

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A BER performance-aware early termination scheme for layered LDPC decoder

Xiao Peng, Satoshi Goto, Dajiang Zhou, 2010, 2010 IEEE Workshop On Signal Processing Systems.

Fast SAO estimation algorithm and its VLSI architecture

Satoshi Goto, Dajiang Zhou, Shinji Kimura, 2014, 2014 IEEE International Conference on Image Processing (ICIP).

A high throughput CABAC encoder design

Satoshi Goto, Dajiang Zhou, Wei Fei, 2011, 2011 IEEE 7th International Colloquium on Signal Processing and its Applications.

A Low-Power VLSI Architecture for HEVC De-Quantization and Inverse Transform

Dajiang Zhou, Shinji Kimura, Heming Sun, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An FPGA-based 4K UHDTV H.264/AVC video decoder

Satoshi Goto, Dajiang Zhou, Yue Pan, 2013, 2013 IEEE International Conference on Multimedia and Expo Workshops (ICMEW).

A 530Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2010, 2010 Symposium on VLSI Circuits.

High-Performance H.264/AVC Intra-Prediction Architecture for Ultra High Definition Video Applications

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A High Parallelism LDPC Decoder with an Early Stopping Criterion for WiMax and WiFi Application

Dajiang Zhou, Satoshi Goto, Xiao Peng, 2010, IPSJ Trans. Syst. LSI Des. Methodol..

Low-Power Motion Estimation Processor with 3D Stacked Memory

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

High profile intra prediction architecture for H.264

Jinjia Zhou, Dajiang Zhou, Xun He, 2009, 2009 International SoC Design Conference (ISOCC).

An advanced hierarchical motion estimation scheme with lossless frame recompression for ultra high definition video coding

Satoshi Goto, Dajiang Zhou, Peilin Liu, 2010, 2010 IEEE International Conference on Multimedia and Expo.

Live demonstration: FPGA based 3840×2160 video decoding and displaying system

Satoshi Goto, Dajiang Zhou, Haoming Zhang, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Sparseness Ratio Allocation and Neuron Re-pruning for Neural Networks Compression

Jinjia Zhou, Dajiang Zhou, Li Guo, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

CNN-MERP: An FPGA-based memory-efficient reconfigurable processor for forward and backward propagation of convolutional neural networks

Dajiang Zhou, Shihao Wang, Xushen Han, 2016, 2016 IEEE 34th International Conference on Computer Design (ICCD).

A 136 cycles/MB, luma-chroma parallelized H.264/AVC deblocking filter for QFHD applications

Satoshi Goto, Yu Hong, Jinjia Zhou, 2009, 2009 IEEE International Conference on Multimedia and Expo.

DVB-T2 LDPC decoder with perfect conflict resolution

Xiao Peng, Satoshi Goto, Dajiang Zhou, 2012, Proceedings of Technical Program of 2012 VLSI Design, Automation and Test.

DRAM Bandwidth Optimized Design for High-Throughput Video Decoder Chips

Dajiang Zhou, Dajiang Zhou, 2010 .

A 610 Mbin/s CABAC decoder for H.265/HEVC level 6.1 applications

Satoshi Goto, Jinjia Zhou, Yijin Zhao, 2014, 2014 IEEE International Conference on Image Processing (ICIP).

A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip

Dajiang Zhou, Zhixiang Chen, Qian Xie, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Lossless embedded compression using multi-mode DPCM & averaging prediction for HEVC-like video codec

Satoshi Goto, Dajiang Zhou, Li Guo, 2013, 21st European Signal Processing Conference (EUSIPCO 2013).

An SDRAM controller optimized for high definition video coding application

Dajiang Zhou, Peilin Liu, Jiayi Zhu, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Fast Algorithm and VLSI Architecture of Rate Distortion Optimization in H.265/HEVC

Satoshi Goto, Dajiang Zhou, Shinji Kimura, 2017, IEEE Transactions on Multimedia.

A full layer parallel QC-LDPC decoder for WiMAX and Wi-Fi

Wenchao Zhang, Dajiang Zhou, Xuefei Bai, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

Approximate-DCT-Derived Measurement Matrices with Row-Operation-Based Measurement Compression and its VLSI Architecture for Compressed Sensing

Satoshi Goto, Jian-Bin Zhou, Dajiang Zhou, 2018, IEICE Trans. Electron..

Motion compensation architecture for 8K UHDTV HEVC decoder

Satoshi Goto, Dajiang Zhou, Shihao Wang, 2014, 2014 IEEE International Conference on Multimedia and Expo (ICME).

High Performance VLSI Architecture of H.265/HEVC Intra Prediction for 8K UHDTV Video Decoder

Satoshi Goto, Jian-Bin Zhou, Dajiang Zhou, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An independent bandwidth reduction device for HEVC VLSI video system

Satoshi Goto, Dajiang Zhou, Li Guo, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

An early stopping criterion for decoding LDPC codes in WiMAX and WiFi standards

Xiao Peng, Satoshi Goto, Dajiang Zhou, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

A high-performance CABAC encoder architecture for HEVC and H.264/AVC

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2013, 2013 IEEE International Conference on Image Processing.

A highly efficient inverse transform architecture for multi-standard HDTV decoder

Dajiang Zhou, Peilin Liu, Yu Hong, 2009, 2009 IEEE 8th International Conference on ASIC.

DVB-T2 LDPC decoder with perfect conflict resolution

Xiao Peng, Satoshi Goto, Dajiang Zhou, 2012, VLSI-DAT.

A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2011, IEEE Journal of Solid-State Circuits.

Intra prediction architecture for H.264/AVC QFHD encoder

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2010, 28th Picture Coding Symposium.

A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65nm CMOS

Xiao Peng, Satoshi Goto, Dajiang Zhou, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Distortion Control and Optimization for Lossy Embedded Compression in Video Codec System

Satoshi Goto, Dajiang Zhou, Li Guo, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Merge mode based fast inter prediction for HEVC

Dajiang Zhou, Shinji Kimura, Heming Sun, 2015, 2015 Visual Communications and Image Processing (VCIP).

A low power 720p motion estimation processor with 3D stacked memory

Satoshi Goto, Jinjia Zhou, Dajiang Zhou, 2014, 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC).

Perceptual Image Compression using Relativistic Average Least Squares GANs

Dajiang Zhou, Shihao Wang, Xiongxin Zhao, 2021, 2021 IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops (CVPRW).

A New Reference Frame Recompression Algorithm and Its VLSI Architecture for UHDTV Video Codec

Satoshi Goto, Dajiang Zhou, Li Guo, 2014, IEEE Transactions on Multimedia.