Sarang Kazeminia

发表

Bulk controlled offset cancellation mechanism for single-stage latched comparator

Sina Mahdavi, Sarang Kazeminia, Reza Gholamnejad, 2016, 2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems.

A 17 MS/s SAR ADC with energy-efficient switching strategy

Sina Mahdavi, Khayrollah Hadidi, Sarang Kazeminia, 2020 .

A low-jitter leakage-free digitally calibrated phase locked loop

Sarang Kazeminia, Arefeh Soltani, 2020, Comput. Electr. Eng..

A Wide-Range Low-Jitter PLL Based on Fast-Response VCO and Simplified Straightforward Methodology of Loop Stabilization in Integer-N PLLs

Abdollah Khoei, Khayrollah Hadidi, Sarang Kazeminia, 2015, J. Circuits Syst. Comput..

A fast-locking low-jitter digitally-enhanced DLL dynamically controlled for loop-gain and stability

Arash Hejazi, Sarang Kazeminia, Roozbeh Abdollahi, 2018 .

Producing flat supply voltage using a temperature-compensated BGR within LDO regulator loop

Khayrollah Hadidi, Sarang Kazeminia, Nahid Salehjoo, 2014, 2014 22nd Iranian Conference on Electrical Engineering (ICEE).

Speed enhancement and kickback noise reduction in single-stage latched comparator improved for high-speed and low-noise analogue-to-digital converters

Khayrollah Hadidi, Sarang Kazeminia, Obalit Shino, 2017 .

A Novel Open Loop Structure for Phase Shifting and Frequency Synthesizing

Abdollah Khoei, Khayrollah Hadidi, Sarang Kazeminia, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Wide-range 16-phases DLL based on improved dead-zone phase detector and reduced gain charge pump

Khayrollah Hadidi, Sarang Kazeminia, Sobhan Sofi Mowloodi, 2014, 2014 22nd Iranian Conference on Electrical Engineering (ICEE).

A foreground-liked continuous-time offset cancellation strategy for open-loop inter-stage amplifiers in high-resolution ADCs

Khayrollah Hadidi, Sarang Kazeminia, 2018, Integr..

A 800MS/s, 150µV input-referred offset single-stage latched comparator

Sina Mahdavi, Sarang Kazeminia, 2016, 2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems.

A digitally assisted 20MHz–600MHz 16-phase DLL enhanced with dynamic gain control loop

Arash Hejazi, Sarang Kazeminia, Roozbeh Abdollahi, 2015, 2015 European Conference on Circuit Theory and Design (ECCTD).

A real-time pseudo-background gain calibration strategy for residue amplifiers of pipeline ADCs

Sarang Kazeminia, 2019, Integr..

Design of high-speed high-precision voltage-mode MAX-MIN circuits with low area and low power consumption

Abdollah Khoei, Khayrollah Hadidi, Sarang Kazeminia, 2009, 2009 European Conference on Circuit Theory and Design.

High Speed High Precision Voltage-Mode MAX and MIN Circuits

Abdollah Khoei, Khayrollah Hadidi, Sarang Kazeminia, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

Improved single-stage kickback-rejected comparator for high speed and low noise flash ADCs

Khayrollah Hadidi, Sarang Kazeminia, Obalit Shino, 2013, 2013 European Conference on Circuit Theory and Design (ECCTD).

A 10-bit 50MS/s pipeline ADC based on kickback-rejected comparators improved for small-amplitude inputs

Abdollah Khoei, Khayrollah Hadidi, Sarang Kazeminia, 2014, 2014 22nd Iranian Conference on Electrical Engineering (ICEE).

Effect of bandgap energy temperature dependence on thermal coefficient of bandgap reference voltage

Abdollah Khoei, Khayrollah Hadidi, Sarang Kazeminia, 2011, 2011 20th European Conference on Circuit Theory and Design (ECCTD).

High Speed High Precision voltage-Mode Max and Min Circuits

Abdollah Khoei, Khayrollah Hadidi, Sarang Kazeminia, 2007, J. Circuits Syst. Comput..

Highly-matched sub-ADC cells for pipeline analogue-to-digital converters

Sina Mahdavi, Sarang Kazeminia, 2019 .

High-speed low-power Single-Stage latched-comparator with improved gain and kickback noise rejection

Abdollah Khoei, Khayrollah Hadidi, Morteza Mousazadeh, 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

Dual-path linearization technique for bandwidth enhancement in SAH circuits

Sarang Kazeminia, Amir Laal Shahsavar, 2019 .

An 8-bit 2.5GS/s D/A converter in 0.35µ CMOS technology with improved pipeline structure

Abdollah Khoei, Khayrollah Hadidi, Sarang Kazeminia, 2010, 2010 18th Iranian Conference on Electrical Engineering.

A 250MHz to 4GHz adaptive bias tuned PLL for low-jitter applications based on a fast response VCO oscillating cells

Abdollah Khoei, Khayrollah Hadidi, Sarang Kazeminia, 2014, 2014 22nd Iranian Conference on Electrical Engineering (ICEE).

A 500 MS/s 600 µW 300 µm2 Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35 µm 3.3 v CMOS Process

Abdollah Khoei, Khayrollah Hadidi, Morteza Mousazadeh, 2011, IEICE Trans. Electron..

Single-stage offset-cancelled latched comparator scheduled by multi-level control on reset switch

Sarang Kazeminia, Arefeh Soltani, 2016, 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Digitally-assisted gain calibration strategy for open-loop residue amplifiers in pipeline ADCs

Sarang Kazeminia, Arefeh Soltani, 2016, 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

An extendable global clock high-speed binary counter compatible to the FPGA CLBs

Faeze Noruzpur, Sarang Kazeminia, Maryam Ghafoorzadeh, 2017, 2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems.

Modelling of Friction Stir Extrusion using Artificial Neural Network (ANN)

Ali Ansari, Dong Lin, Sarang Kazeminia, 2018 .

A low jitter 110MHz 16-phase delay locked loop based on a simple and sensitive phase detector

Abdollah Khoei, Khayrollah Hadidi, Sarang Kazeminia, 2013, 2013 21st Iranian Conference on Electrical Engineering (ICEE).

On matching properties of R-2R ladders in high performance digital-to-analog converters

Abdollah Khoei, Khayrollah Hadidi, Sarang Kazeminia, 2010, 2010 18th Iranian Conference on Electrical Engineering.

An Open Loop Phase Shifter and Frequency Synthesizer

Khayrollah Hadidi, Sarang Kazeminia, 2007, 2007 14th IEEE International Conference on Electronics, Circuits and Systems.

Digitally-assisted offset cancellation technique for open loop residue amplifiers in high-resolution and high-speed ADCs

Sina Mahdavi, Khayrollah Hadidi, Sarang Kazeminia, 2016, 2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems.

Programmable incrementing/decrementing binary accumulator for high-speed calibration loops

Sarang Kazeminia, Arefeh Soltani, Roozbeh Abdollahi, 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).

A 80-MHz-to-410-MHz 16-Phases DLL Based on Improved Dead-Zone Open-Loop Phase Detector and Reduced-Gain Charge Pump

Khayrollah Hadidi, Sarang Kazeminia, Sobhan Sofi Mowloodi, 2015, J. Circuits Syst. Comput..

Robust sliding-mode control for maximum power point tracking of photovoltaic power systems with quantized input signal

Mortaza Aliasghary, Sarang Kazeminia, Hojjat Aminnejhad, 2021, Optik.

Reanalyzing the basic bandgap reference voltage circuit considering thermal dependence of bandgap energy

Abdollah Khoei, Khayrollah Hadidi, Sarang Kazeminia, 2014 .