Ji Hwan Park

22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST

Ji Hwan Park, Jiho Choi, Seong Hee Lee, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization

Seokwoo Choi, T. Hwang, Kyungjun Cho, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

C-QM: A Practical Quality Model for Evaluating COTS Components

Ji Hwan Park, Soo Dong Kim, Soo Dong Kim, 2003, Applied Informatics.