Daeyong Shim

22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST

Ji Hwan Park, Jiho Choi, Seong Hee Lee, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

4-Slot, 8-Drop Impedance-Matched Bidirectional Multidrop DQ Bus With a 4.8-Gb/s Memory Controller Transceiver

Deog-Kyoon Jeong, Jung-Hoon Chun, Woo-Yeol Shin, 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Fast and Accurate Power Distribution Network Modeling of a Silicon Interposer for 2.5-D/3-D ICs With Multiarray TSVs

Joungho Kim, Junyong Park, Kyungjun Cho, 2019, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Holistic approaches to memory solutions for the Autonomous Driving Era

Il Memming Park, Yongkee Kwon, Chunseok Jeong, 2022, 2022 IEEE International Symposium on Circuits and Systems (ISCAS).

A Process-Variation-Tolerant On-Chip CMOS Thermometer for Auto Temperature Compensated Self-Refresh of Low-Power Mobile DRAM

Suhwan Kim, Deog-Kyoon Jeong, Hyunjoong Lee, 2013, IEEE Journal of Solid-State Circuits.

A 1.2V 64Gb 341GB/S HBM2 stacked DRAM with spiral point-to-point TSV structure and improved bank group data control

Jin-Hee Cho, Seokwoo Choi, Jinkook Kim, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).