Chih-Tsun Huang

发表

A Simulation-Based Methodology for SRAM Defect Analysis and Diagnosis

Rei-Fu Huang, J. Yeh, Chih-Wea Wang, 2022 .

Error catch and analysis for semiconductor memories using March tests

Cheng-Wen Wu, Chih-Tsun Huang, Chi-Feng Wu, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Simulation-based test algorithm generation and port scheduling for multi-port memories

Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, 2001, Proceedings - Design Automation Conference.

High-speed easily testable Galois-field inverter

Chih-Tsun Huang, Cheng-Wen Wu, 2000 .

A Programmable BIST Core for Embedded DRAM

Cheng-Wen Wu, Chih-Tsun Huang, Jing-Reng Huang, 1999, IEEE Des. Test Comput..

Test scheduling and test access architecture optimization for system-on-chip

Youn-Long Lin, Cheng-Wen Wu, Chih-Tsun Huang, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

An SOC test integration platform and its industrial realization

Chih-Wea Wang, Chih-Tsun Huang, Kuo-Liang Cheng, 2004, 2004 International Conferce on Test.

High-Performance Architecture for Elliptic Curve Cryptography over Prime Fields on FPGAs

Chih-Tsun Huang, Jyu-Yuan Lai, Chih-Tsun Huang, 2012 .

Optimization of AI SoC with Compiler-assisted Virtual Design Platform

Shih-Chieh Chang, Chih-Tsun Huang, Juin-Ming Lu, 2023, ISPD.

Tile-Based Architecture Exploration for Convolutional Accelerators in Deep Neural Networks

Chih-Tsun Huang, Jing-Jia Liou, Juin-Ming Lu, 2021, 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS).

Efficient Dynamic Fixed-Point Quantization of CNN Inference Accelerators for Edge Devices

Yueh-Chi Wu, Chih- Tsun Huang, Chih-Tsun Huang, 2019, 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Data Locality Optimization of Depthwise Separable Convolutions for CNN Inference Accelerators

Chih-Tsun Huang, Hao-Ning Wu, Chih-Tsun Huang, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Efficient Segment-wise Pruning for DCNN Inference Accelerators

J. Liou, Chih-Tsun Huang, Juin-Ming Lu, 2022, 2022 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Soc Testing and Design for Testability

Cheng-Wen Wu, Chih-Tsun Huang, Chih-Tsun Huang, 2006 .

Diagonal test and diagnostic schemes for flash memories

Jen-Chieh Yeh, Cheng-Wen Wu, Chih-Tsun Huang, 2002, Proceedings. International Test Conference.

BRAINS: a BIST compiler for embedded memories

Ming-Chang Tsai, Cheng-Wen Wu, Chih-Tsun Huang, 2000, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

RAMSES-FT: a fault simulator for flash memory testing and diagnostics

Jen-Chieh Yeh, Cheng-Wen Wu, Chih-Tsun Huang, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

Energy-Adaptive Dual-Field Processor for High-Performance Elliptic Curve Cryptographic Applications

Chih-Tsun Huang, Jyu-Yuan Lai, Chih-Tsun Huang, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

High-performance architecture for Elliptic Curve Cryptography over binary field

Chih-Tsun Huang, Kai-Hsiang Yang, Jyu-Yuan Lai, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

IoT: Source of test challenges

Mario Konijnenburg, Yervant Zorian, Erik Jan Marinissen, 2016, 2016 21th IEEE European Test Symposium (ETS).

Built-in redundancy analysis for memory yield improvement

Jin-Fu Li, Cheng-Wen Wu, Chih-Tsun Huang, 2003, IEEE Trans. Reliab..

A high-throughput low-cost AES cipher chip

Cheng-Wen Wu, Chih-Tsun Huang, Tsung-Fu Lin, 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

Single- and Multi-core Configurable AES Architectures for Flexible Security

Cheng-Wen Wu, Chih-Tsun Huang, Chih-Pin Su, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design of low-cost elliptic curve cryptographic engines for ubiquitous security

Chih-Tsun Huang, Hsin-Yu Ting, Chih-Tsun Huang, 2014, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test.

Elixir: High-Throughput Cost-Effective Dual-Field Processors and the Design Framework for Elliptic Curve Cryptography

Chih-Tsun Huang, Jyu-Yuan Lai, Chih-Tsun Huang, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Hardware/software co-designed accelerator for vector graphics applications

Yeh-Ching Chung, Chih-Tsun Huang, Yi-Cheng Chen, 2011, 2011 IEEE 9th Symposium on Application Specific Processors (SASP).

A word-based RSA crypto-processor with enhanced pipeline performance

Cheng-Wen Wu, Chih-Tsun Huang, Chen-Hsing Wang, 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.

Test and diagnosis of word-oriented multiport memories

Cheng-Wen Wu, Chih-Tsun Huang, Kuo-Liang Cheng, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

Fault simulation and test algorithm generation for random accessmemories

Cheng-Wen Wu, Chih-Tsun Huang, Chi-Feng Wu, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A built-in self-test and self-diagnosis scheme for heterogeneous SRAM clusters

Shi-Yu Huang, Cheng-Wen Wu, Chih-Tsun Huang, 2001, Proceedings 10th Asian Test Symposium.

Simulation-based test algorithm generation for random access memories

Cheng-Wen Wu, Chih-Tsun Huang, Chi-Feng Wu, 2000, Proceedings 18th IEEE VLSI Test Symposium.

RAMSES: a fast memory fault simulator

Cheng-Wen Wu, Chih-Tsun Huang, Chi-Feng Wu, 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).