Weiguang Sheng

发表

A contactless testing methodology for pre-bond interposer

Jianfei Jiang, Weiguang Sheng, Qin Wang, 2015, 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS).

Parallel SER analysis for combinational and sequential standard cell circuits

Zhigang Mao, Weiguang Sheng, Jian-Fei Jiang, 2016, Microelectron. J..

Fail-Slow at Scale

Robert B. Ross, Kevin Harms, Robert Ricci, 2018, ACM Trans. Storage.

A Thermal-Aware Task Mapping Algorithm for Coarse Grain Reconfigurable Computing System

Zhigang Mao, Weiguang Sheng, Weifeng He, 2012 .

An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling

Liyi Xiao, Zhigang Mao, Weiguang Sheng, 2008, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008).

Automatic compilation flow for a coarse-grained reconfigurable processor

Hao Wang, Weiguang Sheng, Weifeng He, 2011, 2011 9th IEEE International Conference on ASIC.

Parasitic Parameters Impacts Investigation on Soft Error Rate by a Circuit Level Framework

Zhigang Mao, Weiguang Sheng, Zhongyuan Zhao, 2015, 2015 IEEE 21st Pacific Rim International Symposium on Dependable Computing (PRDC).

A pre-emphasis circuit design for high speed on-chip global interconnect

Zhigang Mao, Weiguang Sheng, Weifeng He, 2012, 2012 IEEE International Symposium on Circuits and Systems.

A novel soft error sensitivity characterization technique based on simulated fault injection and constrained association analysis

Liyi Xiao, Zhigang Mao, Weiguang Sheng, 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

Full Automatic Task Compilation Flow from C to REmus Coarse Grain Reconfigurable Media Processor

Zhigang Mao, Jianfei Jiang, Weiguang Sheng, 2011 .

Versatile and Efficient Techniques for Speeding-Up Circuit Level Simulated Fault-Injection Campaigns

Liyi Xiao, Zhigang Mao, Weiguang Sheng, 2008, 2008 14th IEEE Pacific Rim International Symposium on Dependable Computing.

mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator

Zhigang Mao, Weiguang Sheng, Zhongyuan Zhao, 2019, 2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

System level power consumption modeling and optimization for coarse-grained reconfigurable architectures

Weiguang Sheng, Zhongyuan Zhao, Weifeng He, 2016, 2016 International Conference on Integrated Circuits and Microsystems (ICICM).

The construction and management of template library for coarse-grained reconfigurable system

Weiguang Sheng, Qin Wang, Xiao Cui, 2010, 2010 International Conference on Computer Application and System Modeling (ICCASM 2010).

Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects

Zhigang Mao, Weiguang Sheng, Qin Wang, 2016, J. Circuits Syst. Comput..

Ship detection based on fused features and rebuilt YOLOv3 networks in optical remote-sensing images

Guanghui He, Jianfei Jiang, Weiguang Sheng, 2021 .

Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling

Weiguang Sheng, Qin Wang, Pengfei Ye, 2020, IEEE Transactions on Parallel and Distributed Systems.

MBSS:A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs

Zhigang Mao, Weiguang Sheng, Zhongyuan Zhao, 2018, 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

Fail-Slow at Scale: Evidence of Hardware Performance Faults in Large Production Systems

Robert B. Ross, Robert Ricci, Weiguang Sheng, 2018, FAST.

Lung Nodule Detection in CT Images Using a Raw Patch-Based Convolutional Neural Network

Weiguang Sheng, Jia Huang, Qin Wang, 2019, Journal of Digital Imaging.

A static-placement, dynamic-issue framework for CGRA loop accelerator

Zhigang Mao, Weiguang Sheng, Zhongyuan Zhao, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm

Zhigang Mao, Weiguang Sheng, Weifeng He, 2012, 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum.

Priority Branches for Ship Detection in Optical Remote Sensing Images

Weiguang Sheng, Qin Wang, Naifeng Jing, 2020, Remote. Sens..

Designing ARINC653 Partition Constrained Scheduling for Secure Real Time Embedded Avionics

Yongxin Zhu, Han Song, Weiguang Sheng, 2015, 2015 IEEE 2nd International Conference on Cyber Security and Cloud Computing.

An automatic translation and parallelization system for general purpose reconfigurable processor

Weiguang Sheng, Weifeng He, Fengshuo Tian, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

Delay hidden techniques based on configuration contexts reuse and differential reconfiguration in coarse-grained reconfigurable processor

Zhigang Mao, Weiguang Sheng, Haopeng Liu, 2013, 2013 IEEE 10th International Conference on ASIC.

Optimizing the data placement and transformation for multi-bank CGRA computing system

Zhigang Mao, Weiguang Sheng, Qin Wang, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration

Guanghui He, Weiguang Sheng, Naifeng Jing, 2020, ACM Great Lakes Symposium on VLSI.

Resource-saving compile flow for coarse-grained reconfigurable architectures

Zhigang Mao, Weiguang Sheng, Zhongyuan Zhao, 2015, 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

A New Cellular-Based Redundant TSV Structure for Clustered Faults

Jianfei Jiang, Weiguang Sheng, Naifeng Jing, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An automatic parallelizer for Coarse-Grained Reconfigurable processor

Weiguang Sheng, Zhongyuan Zhao, Weifeng He, 2016, 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

A clock-less transceiver for global interconnect

Xu Wang, Zhigang Mao, Weiguang Sheng, 2011, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip.

Efficient temporal task partition for coarse-grain reconfigurable systems based on Simulated Annealing Genetic Algorithm

Zhigang Mao, Weiguang Sheng, Yifan Zhou, 2011, 2011 9th IEEE International Conference on ASIC.

Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm

Liyi Xiao, Zhigang Mao, Weiguang Sheng, 2009, 2009 46th ACM/IEEE Design Automation Conference.

Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture

Zhigang Mao, Weiguang Sheng, Jianfei Jiang, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture

Zhigang Mao, Weiguang Sheng, Jianfei Jiang, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A Mapping Method for Reconfigurable Array based on Decoupled DataFlow

Zhigang Mao, Weiguang Sheng, Jianfei Jiang, 2021, 2021 7th IEEE Intl Conference on Big Data Security on Cloud (BigDataSecurity), IEEE Intl Conference on High Performance and Smart Computing, (HPSC) and IEEE Intl Conference on Intelligent Data and Security (IDS).

Weiguang Sheng, Pengfei Ye, Qin Wang, 2021, Electronics.